The ADD and ADDK (and all variants) instructions where flip-flopped in the MBlaze backend. This bug fix makes 64-bit math work on the MBlaze backend.
llvm-svn: 121649
diff --git a/llvm/lib/Target/MBlaze/MBlazeAsmBackend.cpp b/llvm/lib/Target/MBlaze/MBlazeAsmBackend.cpp
index 0d39d60..8037c4e 100644
--- a/llvm/lib/Target/MBlaze/MBlazeAsmBackend.cpp
+++ b/llvm/lib/Target/MBlaze/MBlazeAsmBackend.cpp
@@ -61,7 +61,7 @@
static unsigned getRelaxedOpcode(unsigned Op) {
switch (Op) {
default: return Op;
- case MBlaze::ADDI: return MBlaze::ADDI32;
+ case MBlaze::ADDIK: return MBlaze::ADDIK32;
case MBlaze::ORI: return MBlaze::ORI32;
case MBlaze::BRLID: return MBlaze::BRLID32;
}
diff --git a/llvm/lib/Target/MBlaze/MBlazeFrameInfo.cpp b/llvm/lib/Target/MBlaze/MBlazeFrameInfo.cpp
index cef82cc..7789723 100644
--- a/llvm/lib/Target/MBlaze/MBlazeFrameInfo.cpp
+++ b/llvm/lib/Target/MBlaze/MBlazeFrameInfo.cpp
@@ -187,7 +187,7 @@
int RAOffset = MBlazeFI->getRAStackOffset();
// Adjust stack : addi R1, R1, -imm
- BuildMI(MBB, MBBI, DL, TII.get(MBlaze::ADDI), MBlaze::R1)
+ BuildMI(MBB, MBBI, DL, TII.get(MBlaze::ADDIK), MBlaze::R1)
.addReg(MBlaze::R1).addImm(-StackSize);
// swi R15, R1, stack_loc
@@ -242,7 +242,7 @@
// addi R1, R1, imm
if (StackSize) {
- BuildMI(MBB, MBBI, dl, TII.get(MBlaze::ADDI), MBlaze::R1)
+ BuildMI(MBB, MBBI, dl, TII.get(MBlaze::ADDIK), MBlaze::R1)
.addReg(MBlaze::R1).addImm(StackSize);
}
}
diff --git a/llvm/lib/Target/MBlaze/MBlazeISelDAGToDAG.cpp b/llvm/lib/Target/MBlaze/MBlazeISelDAGToDAG.cpp
index 9924e67..2da8a59 100644
--- a/llvm/lib/Target/MBlaze/MBlazeISelDAGToDAG.cpp
+++ b/llvm/lib/Target/MBlaze/MBlazeISelDAGToDAG.cpp
@@ -210,7 +210,7 @@
int FI = dyn_cast<FrameIndexSDNode>(Node)->getIndex();
EVT VT = Node->getValueType(0);
SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);
- unsigned Opc = MBlaze::ADDI;
+ unsigned Opc = MBlaze::ADDIK;
if (Node->hasOneUse())
return CurDAG->SelectNodeTo(Node, Opc, VT, TFI, imm);
return CurDAG->getMachineNode(Opc, dl, VT, TFI, imm);
diff --git a/llvm/lib/Target/MBlaze/MBlazeISelLowering.cpp b/llvm/lib/Target/MBlaze/MBlazeISelLowering.cpp
index fb6fb54..ad7222a 100644
--- a/llvm/lib/Target/MBlaze/MBlazeISelLowering.cpp
+++ b/llvm/lib/Target/MBlaze/MBlazeISelLowering.cpp
@@ -268,7 +268,7 @@
.addImm(31);
unsigned IVAL = R.createVirtualRegister(MBlaze::GPRRegisterClass);
- BuildMI(BB, dl, TII->get(MBlaze::ADDI), IVAL)
+ BuildMI(BB, dl, TII->get(MBlaze::ADDIK), IVAL)
.addReg(MI->getOperand(1).getReg())
.addImm(0);
@@ -297,7 +297,7 @@
else
llvm_unreachable("Cannot lower unknown shift instruction");
- BuildMI(loop, dl, TII->get(MBlaze::ADDI), NAMT)
+ BuildMI(loop, dl, TII->get(MBlaze::ADDIK), NAMT)
.addReg(SAMT)
.addImm(-1);
diff --git a/llvm/lib/Target/MBlaze/MBlazeInstrFPU.td b/llvm/lib/Target/MBlaze/MBlazeInstrFPU.td
index 8f37332..094de5c 100644
--- a/llvm/lib/Target/MBlaze/MBlazeInstrFPU.td
+++ b/llvm/lib/Target/MBlaze/MBlazeInstrFPU.td
@@ -143,74 +143,74 @@
// SET_CC operations
let Predicates=[HasFPU] in {
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETEQ),
- (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
+ (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(FCMP_EQ GPR:$L, GPR:$R), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETNE),
- (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
+ (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(FCMP_EQ GPR:$L, GPR:$R), 1)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOEQ),
- (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
+ (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(FCMP_EQ GPR:$L, GPR:$R), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETONE),
- (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
+ (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(XOR (FCMP_UN GPR:$L, GPR:$R),
(FCMP_EQ GPR:$L, GPR:$R)), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETONE),
- (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
+ (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(OR (FCMP_UN GPR:$L, GPR:$R),
(FCMP_EQ GPR:$L, GPR:$R)), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETGT),
- (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
+ (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(FCMP_GT GPR:$L, GPR:$R), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETLT),
- (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
+ (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(FCMP_LT GPR:$L, GPR:$R), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETGE),
- (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
+ (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(FCMP_GE GPR:$L, GPR:$R), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETLE),
- (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
+ (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(FCMP_LE GPR:$L, GPR:$R), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOGT),
- (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
+ (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(FCMP_GT GPR:$L, GPR:$R), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOLT),
- (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
+ (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(FCMP_LT GPR:$L, GPR:$R), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOGE),
- (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
+ (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(FCMP_GE GPR:$L, GPR:$R), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOLE),
- (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
+ (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(FCMP_LE GPR:$L, GPR:$R), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUEQ),
- (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
+ (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(OR (FCMP_UN GPR:$L, GPR:$R),
(FCMP_EQ GPR:$L, GPR:$R)), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUNE),
- (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
+ (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(FCMP_NE GPR:$L, GPR:$R), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUGT),
- (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
+ (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(OR (FCMP_UN GPR:$L, GPR:$R),
(FCMP_GT GPR:$L, GPR:$R)), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETULT),
- (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
+ (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(OR (FCMP_UN GPR:$L, GPR:$R),
(FCMP_LT GPR:$L, GPR:$R)), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUGE),
- (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
+ (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(OR (FCMP_UN GPR:$L, GPR:$R),
(FCMP_GE GPR:$L, GPR:$R)), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETULE),
- (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
+ (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(OR (FCMP_UN GPR:$L, GPR:$R),
(FCMP_LE GPR:$L, GPR:$R)), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETO),
- (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
+ (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(FCMP_UN GPR:$L, GPR:$R), 1)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUO),
- (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
+ (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(FCMP_UN GPR:$L, GPR:$R), 2)>;
}
diff --git a/llvm/lib/Target/MBlaze/MBlazeInstrInfo.td b/llvm/lib/Target/MBlaze/MBlazeInstrInfo.td
index 9bda006..8b6420d 100644
--- a/llvm/lib/Target/MBlaze/MBlazeInstrInfo.td
+++ b/llvm/lib/Target/MBlaze/MBlazeInstrInfo.td
@@ -327,9 +327,9 @@
//===----------------------------------------------------------------------===//
let isCommutable = 1, isAsCheapAsAMove = 1 in {
- def ADD : Arith<0x00, 0x000, "add ", add, IIAlu>;
+ def ADD : Arith<0x00, 0x000, "add ", addc, IIAlu>;
def ADDC : Arith<0x02, 0x000, "addc ", adde, IIAlu>;
- def ADDK : Arith<0x04, 0x000, "addk ", addc, IIAlu>;
+ def ADDK : Arith<0x04, 0x000, "addk ", add, IIAlu>;
def ADDKC : ArithN<0x06, 0x000, "addkc ", IIAlu>;
def AND : Logic<0x21, 0x000, "and ", and>;
def OR : Logic<0x20, 0x000, "or ", or>;
@@ -343,9 +343,9 @@
def ANDN : ArithN<0x23, 0x000, "andn ", IIAlu>;
def CMP : ArithN<0x05, 0x001, "cmp ", IIAlu>;
def CMPU : ArithN<0x05, 0x003, "cmpu ", IIAlu>;
- def RSUB : ArithR<0x01, 0x000, "rsub ", sub, IIAlu>;
+ def RSUB : ArithR<0x01, 0x000, "rsub ", subc, IIAlu>;
def RSUBC : ArithR<0x03, 0x000, "rsubc ", sube, IIAlu>;
- def RSUBK : ArithR<0x05, 0x000, "rsubk ", subc, IIAlu>;
+ def RSUBK : ArithR<0x05, 0x000, "rsubk ", sub, IIAlu>;
def RSUBKC : ArithRN<0x07, 0x000, "rsubkc ", IIAlu>;
}
@@ -589,7 +589,7 @@
}
let isCodeGenOnly=1 in {
- def ADDI32 : ArithI32<0x08, "addi ", simm16, immSExt16>;
+ def ADDIK32 : ArithI32<0x08, "addik ", simm16, immSExt16>;
def ORI32 : LogicI32<0x28, "ori ">;
def BRLID32 : BranchLI<0x2E, 0x14, "brlid ">;
}
@@ -632,11 +632,11 @@
// Small immediates
def : Pat<(i32 0), (ADD (i32 R0), (i32 R0))>;
-def : Pat<(i32 immSExt16:$imm), (ADDI (i32 R0), imm:$imm)>;
+def : Pat<(i32 immSExt16:$imm), (ADDIK (i32 R0), imm:$imm)>;
def : Pat<(i32 immZExt16:$imm), (ORI (i32 R0), imm:$imm)>;
// Arbitrary immediates
-def : Pat<(i32 imm:$imm), (ADDI (i32 R0), imm:$imm)>;
+def : Pat<(i32 imm:$imm), (ADDIK (i32 R0), imm:$imm)>;
// In register sign extension
def : Pat<(sext_inreg GPR:$src, i16), (SEXT16 GPR:$src)>;
@@ -659,34 +659,34 @@
// SET_CC operations
def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETEQ),
- (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
+ (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(CMP GPR:$R, GPR:$L), 1)>;
def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETNE),
- (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
+ (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(CMP GPR:$R, GPR:$L), 2)>;
def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETGT),
- (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
+ (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(CMP GPR:$R, GPR:$L), 3)>;
def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETLT),
- (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
+ (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(CMP GPR:$R, GPR:$L), 4)>;
def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETGE),
- (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
+ (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(CMP GPR:$R, GPR:$L), 5)>;
def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETLE),
- (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
+ (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(CMP GPR:$R, GPR:$L), 6)>;
def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETUGT),
- (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
+ (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(CMPU GPR:$R, GPR:$L), 3)>;
def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETULT),
- (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
+ (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(CMPU GPR:$R, GPR:$L), 4)>;
def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETUGE),
- (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
+ (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(CMPU GPR:$R, GPR:$L), 5)>;
def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETULE),
- (Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
+ (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(CMPU GPR:$R, GPR:$L), 6)>;
// SELECT operations
@@ -765,7 +765,7 @@
def : Pat<(and (i32 GPR:$lh), (not (i32 GPR:$rh))),(ANDN GPR:$lh, GPR:$rh)>;
// Arithmetic with immediates
-def : Pat<(add (i32 GPR:$in), imm:$imm),(ADDI GPR:$in, imm:$imm)>;
+def : Pat<(add (i32 GPR:$in), imm:$imm),(ADDIK GPR:$in, imm:$imm)>;
def : Pat<(or (i32 GPR:$in), imm:$imm),(ORI GPR:$in, imm:$imm)>;
def : Pat<(xor (i32 GPR:$in), imm:$imm),(XORI GPR:$in, imm:$imm)>;
diff --git a/llvm/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp b/llvm/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp
index e7fb788..90ad502 100644
--- a/llvm/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp
+++ b/llvm/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp
@@ -141,7 +141,7 @@
switch (MI.getOpcode()) {
default: break;
- case MBlaze::ADDI32:
+ case MBlaze::ADDIK32:
case MBlaze::ORI32:
case MBlaze::BRLID32:
EmitByte(0x0D, CurByte, OS);
@@ -168,7 +168,7 @@
Fixups.push_back(MCFixup::Create(0,oper.getExpr(),FixupKind));
break;
case MBlaze::ORI32:
- case MBlaze::ADDI32:
+ case MBlaze::ADDIK32:
case MBlaze::BRLID32:
FixupKind = pcrel ? FK_PCRel_4 : FK_Data_4;
Fixups.push_back(MCFixup::Create(0,oper.getExpr(),FixupKind));
diff --git a/llvm/lib/Target/MBlaze/MBlazeRegisterInfo.cpp b/llvm/lib/Target/MBlaze/MBlazeRegisterInfo.cpp
index 891e189..45da9ea 100644
--- a/llvm/lib/Target/MBlaze/MBlazeRegisterInfo.cpp
+++ b/llvm/lib/Target/MBlaze/MBlazeRegisterInfo.cpp
@@ -185,11 +185,11 @@
MachineInstr *New;
if (Old->getOpcode() == MBlaze::ADJCALLSTACKDOWN) {
- New = BuildMI(MF, Old->getDebugLoc(), TII.get(MBlaze::ADDI), MBlaze::R1)
+ New = BuildMI(MF,Old->getDebugLoc(),TII.get(MBlaze::ADDIK),MBlaze::R1)
.addReg(MBlaze::R1).addImm(-Amount);
} else {
assert(Old->getOpcode() == MBlaze::ADJCALLSTACKUP);
- New = BuildMI(MF, Old->getDebugLoc(), TII.get(MBlaze::ADDI), MBlaze::R1)
+ New = BuildMI(MF,Old->getDebugLoc(),TII.get(MBlaze::ADDIK),MBlaze::R1)
.addReg(MBlaze::R1).addImm(Amount);
}