diff --git a/llvm/lib/Target/Alpha/AlphaLLRP.cpp b/llvm/lib/Target/Alpha/AlphaLLRP.cpp
index 7a1b784..0c51bc5 100644
--- a/llvm/lib/Target/Alpha/AlphaLLRP.cpp
+++ b/llvm/lib/Target/Alpha/AlphaLLRP.cpp
@@ -49,6 +49,7 @@
       const TargetInstrInfo *TII = F.getTarget().getInstrInfo();
       bool Changed = false;
       MachineInstr* prev[3] = {0,0,0};
+      DebugLoc dl = DebugLoc::getUnknownLoc();
       unsigned count = 0;
       for (MachineFunction::iterator FI = F.begin(), FE = F.end();
            FI != FE; ++FI) {
@@ -73,7 +74,7 @@
                prev[0] = prev[1];
                prev[1] = prev[2];
                prev[2] = 0;
-               BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31)
+               BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
                  .addReg(Alpha::R31)
                  .addReg(Alpha::R31); 
                Changed = true; nopintro += 1;
@@ -85,10 +86,10 @@
                         MI->getOperand(1).getImm()) {
                prev[0] = prev[2];
                prev[1] = prev[2] = 0;
-               BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31)
+               BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
                  .addReg(Alpha::R31)
                  .addReg(Alpha::R31); 
-               BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31)
+               BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
                  .addReg(Alpha::R31)
                  .addReg(Alpha::R31);
                Changed = true; nopintro += 2;
@@ -99,12 +100,12 @@
                         && prev[2]->getOperand(1).getImm() == 
                         MI->getOperand(1).getImm()) {
                prev[0] = prev[1] = prev[2] = 0;
-               BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
-                 .addReg(Alpha::R31);
-               BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
-                 .addReg(Alpha::R31);
-               BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
-                 .addReg(Alpha::R31);
+               BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
+                 .addReg(Alpha::R31).addReg(Alpha::R31);
+               BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
+                 .addReg(Alpha::R31).addReg(Alpha::R31);
+               BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
+                 .addReg(Alpha::R31).addReg(Alpha::R31);
                Changed = true; nopintro += 3;
                count += 3;
              }
@@ -136,7 +137,7 @@
         if (ub || AlignAll) {
           //we can align stuff for free at this point
           while (count % 4) {
-            BuildMI(MBB, MBB.end(), TII->get(Alpha::BISr), Alpha::R31)
+            BuildMI(MBB, MBB.end(), dl, TII->get(Alpha::BISr), Alpha::R31)
               .addReg(Alpha::R31).addReg(Alpha::R31);
             ++count;
             ++nopalign;