[AMDGPU] Pattern for v_xor3_b32
This also allows three op patterns to use increased constant bus
limit of GFX10.
Differential Revision: https://reviews.llvm.org/D61763
llvm-svn: 360395
diff --git a/llvm/test/CodeGen/AMDGPU/add3.ll b/llvm/test/CodeGen/AMDGPU/add3.ll
index 8984723..cec85d3 100644
--- a/llvm/test/CodeGen/AMDGPU/add3.ll
+++ b/llvm/test/CodeGen/AMDGPU/add3.ll
@@ -1,6 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
+; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
; ===================================================================================
; V_ADD3_U32
@@ -17,6 +18,11 @@
; GFX9: ; %bb.0:
; GFX9-NEXT: v_add3_u32 v0, v0, v1, v2
; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: add3:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: v_add3_u32 v0, v0, v1, v2
+; GFX10-NEXT: ; return to shader part epilog
%x = add i32 %a, %b
%result = add i32 %x, %c
%bc = bitcast i32 %result to float
@@ -36,6 +42,12 @@
; GFX9-NEXT: v_mad_u32_u24 v0, v0, v1, v4
; GFX9-NEXT: v_mad_u32_u24 v0, v2, v3, v0
; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: mad_no_add3:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: v_mad_u32_u24 v0, v0, v1, v4
+; GFX10-NEXT: v_mad_u32_u24 v0, v2, v3, v0
+; GFX10-NEXT: ; return to shader part epilog
%a0 = shl i32 %a, 8
%a1 = lshr i32 %a0, 8
%b0 = shl i32 %b, 8
@@ -69,6 +81,11 @@
; GFX9-NEXT: s_add_i32 s3, s3, s2
; GFX9-NEXT: v_add_u32_e32 v0, s3, v0
; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: add3_vgpr_b:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: v_add3_u32 v0, s3, s2, v0
+; GFX10-NEXT: ; return to shader part epilog
%x = add i32 %a, %b
%result = add i32 %x, %c
%bc = bitcast i32 %result to float
@@ -86,6 +103,11 @@
; GFX9: ; %bb.0:
; GFX9-NEXT: v_add3_u32 v0, v1, v2, v0
; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: add3_vgpr_all2:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: v_add3_u32 v0, v1, v2, v0
+; GFX10-NEXT: ; return to shader part epilog
%x = add i32 %b, %c
%result = add i32 %a, %x
%bc = bitcast i32 %result to float
@@ -103,6 +125,11 @@
; GFX9: ; %bb.0:
; GFX9-NEXT: v_add3_u32 v0, s2, v0, v1
; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: add3_vgpr_bc:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: v_add3_u32 v0, s2, v0, v1
+; GFX10-NEXT: ; return to shader part epilog
%x = add i32 %a, %b
%result = add i32 %x, %c
%bc = bitcast i32 %result to float
@@ -120,6 +147,11 @@
; GFX9: ; %bb.0:
; GFX9-NEXT: v_add3_u32 v0, v0, v1, 16
; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: add3_vgpr_const:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: v_add3_u32 v0, v0, v1, 16
+; GFX10-NEXT: ; return to shader part epilog
%x = add i32 %a, %b
%result = add i32 %x, 16
%bc = bitcast i32 %result to float
@@ -139,6 +171,12 @@
; GFX9-NEXT: v_add3_u32 v0, v0, v1, v2
; GFX9-NEXT: v_mul_lo_u32 v1, v0, v3
; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: add3_multiuse_outer:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: v_add3_u32 v0, v0, v1, v2
+; GFX10-NEXT: v_mul_lo_u32 v1, v0, v3
+; GFX10-NEXT: ; return to shader part epilog
%inner = add i32 %a, %b
%outer = add i32 %inner, %c
%x1 = mul i32 %outer, %x
@@ -160,6 +198,12 @@
; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
; GFX9-NEXT: v_add_u32_e32 v1, v0, v2
; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: add3_multiuse_inner:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1
+; GFX10-NEXT: v_add_nc_u32_e32 v1, v0, v2
+; GFX10-NEXT: ; return to shader part epilog
%inner = add i32 %a, %b
%outer = add i32 %inner, %c
%r1 = insertelement <2 x i32> undef, i32 %inner, i32 0
@@ -190,6 +234,15 @@
; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: add3_uniform_vgpr:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: v_add_f32_e64 v1, s3, 2.0
+; GFX10-NEXT: v_add_f32_e64 v2, s2, 1.0
+; GFX10-NEXT: v_add_f32_e64 v0, 0x40400000, s4
+; GFX10-NEXT: v_add_nc_u32_e32 v1, v2, v1
+; GFX10-NEXT: v_add_nc_u32_e32 v0, v1, v0
+; GFX10-NEXT: ; return to shader part epilog
%a1 = fadd float %a, 1.0
%b2 = fadd float %b, 2.0
%c3 = fadd float %c, 3.0