[Hexagon] Reorganize and update instruction patterns
llvm-svn: 316228
diff --git a/llvm/test/CodeGen/Hexagon/addrmode-indoff.ll b/llvm/test/CodeGen/Hexagon/addrmode-indoff.ll
index 6ea2b3d..274add3 100644
--- a/llvm/test/CodeGen/Hexagon/addrmode-indoff.ll
+++ b/llvm/test/CodeGen/Hexagon/addrmode-indoff.ll
@@ -3,72 +3,90 @@
; Bug 6840. Use absolute+index addressing.
@ga = common global [1024 x i8] zeroinitializer, align 8
-@gb = common global [1024 x i8] zeroinitializer, align 8
-; CHECK: memub(r{{[0-9]+}}{{ *}}<<{{ *}}#0{{ *}}+{{ *}}##ga)
-define zeroext i8 @lf2(i32 %i) nounwind readonly {
+; CHECK-LABEL: test0
+; CHECK: memub(r{{[0-9]+}}+##ga)
+define zeroext i8 @test0(i32 %i) nounwind readonly {
entry:
- %arrayidx = getelementptr inbounds [1024 x i8], [1024 x i8]* @ga, i32 0, i32 %i
- %0 = load i8, i8* %arrayidx, align 1
+ %t = getelementptr inbounds [1024 x i8], [1024 x i8]* @ga, i32 0, i32 %i
+ %0 = load i8, i8* %t, align 1
ret i8 %0
}
-; CHECK: memb(r{{[0-9]+}}{{ *}}<<{{ *}}#0{{ *}}+{{ *}}##gb)
-define signext i8 @lf2s(i32 %i) nounwind readonly {
+; CHECK-LABEL: test1
+; CHECK: memb(r{{[0-9]+}}+##ga)
+define signext i8 @test1(i32 %i) nounwind readonly {
entry:
- %arrayidx = getelementptr inbounds [1024 x i8], [1024 x i8]* @gb, i32 0, i32 %i
- %0 = load i8, i8* %arrayidx, align 1
+ %t = getelementptr inbounds [1024 x i8], [1024 x i8]* @ga, i32 0, i32 %i
+ %0 = load i8, i8* %t, align 1
ret i8 %0
}
-; CHECK: memub(r{{[0-9]+}}{{ *}}<<{{ *}}#2{{ *}}+{{ *}}##ga)
-define zeroext i8 @lf3(i32 %i) nounwind readonly {
+; CHECK-LABEL: test2
+; CHECK: memub(r{{[0-9]+}}<<#1+##ga)
+define zeroext i8 @test2(i32 %i) nounwind readonly {
entry:
- %mul = shl nsw i32 %i, 2
- %arrayidx = getelementptr inbounds [1024 x i8], [1024 x i8]* @ga, i32 0, i32 %mul
- %0 = load i8, i8* %arrayidx, align 1
+ %j = shl nsw i32 %i, 1
+ %t = getelementptr inbounds [1024 x i8], [1024 x i8]* @ga, i32 0, i32 %j
+ %0 = load i8, i8* %t, align 1
ret i8 %0
}
-; CHECK: memb(r{{[0-9]+}}{{ *}}<<{{ *}}#2{{ *}}+{{ *}}##gb)
-define signext i8 @lf3s(i32 %i) nounwind readonly {
+; CHECK-LABEL: test3
+; CHECK: memb(r{{[0-9]+}}<<#1+##ga)
+define signext i8 @test3(i32 %i) nounwind readonly {
entry:
- %mul = shl nsw i32 %i, 2
- %arrayidx = getelementptr inbounds [1024 x i8], [1024 x i8]* @gb, i32 0, i32 %mul
- %0 = load i8, i8* %arrayidx, align 1
+ %j = shl nsw i32 %i, 1
+ %t = getelementptr inbounds [1024 x i8], [1024 x i8]* @ga, i32 0, i32 %j
+ %0 = load i8, i8* %t, align 1
ret i8 %0
}
-; CHECK: memb(r{{[0-9]+}}{{ *}}<<{{ *}}#0{{ *}}+{{ *}}##ga)
-define void @sf4(i32 %i, i8 zeroext %j) nounwind {
+; CHECK-LABEL: test4
+; CHECK: memub(r{{[0-9]+}}<<#2+##ga)
+define zeroext i8 @test4(i32 %i) nounwind readonly {
entry:
- %arrayidx = getelementptr inbounds [1024 x i8], [1024 x i8]* @ga, i32 0, i32 %i
- store i8 %j, i8* %arrayidx, align 1
+ %j = shl nsw i32 %i, 2
+ %t = getelementptr inbounds [1024 x i8], [1024 x i8]* @ga, i32 0, i32 %j
+ %0 = load i8, i8* %t, align 1
+ ret i8 %0
+}
+
+; CHECK-LABEL: test5
+; CHECK: memb(r{{[0-9]+}}<<#2+##ga)
+define signext i8 @test5(i32 %i) nounwind readonly {
+entry:
+ %j = shl nsw i32 %i, 2
+ %t = getelementptr inbounds [1024 x i8], [1024 x i8]* @ga, i32 0, i32 %j
+ %0 = load i8, i8* %t, align 1
+ ret i8 %0
+}
+
+; CHECK-LABEL: test10
+; CHECK: memb(r{{[0-9]+}}+##ga)
+define void @test10(i32 %i, i8 zeroext %v) nounwind {
+entry:
+ %t = getelementptr inbounds [1024 x i8], [1024 x i8]* @ga, i32 0, i32 %i
+ store i8 %v, i8* %t, align 1
ret void
}
-; CHECK: memb(r{{[0-9]+}}{{ *}}<<{{ *}}#0{{ *}}+{{ *}}##gb)
-define void @sf4s(i32 %i, i8 signext %j) nounwind {
+; CHECK-LABEL: test11
+; CHECK: memb(r{{[0-9]+}}<<#1+##ga)
+define void @test11(i32 %i, i8 signext %v) nounwind {
entry:
- %arrayidx = getelementptr inbounds [1024 x i8], [1024 x i8]* @gb, i32 0, i32 %i
- store i8 %j, i8* %arrayidx, align 1
+ %j = shl nsw i32 %i, 1
+ %t = getelementptr inbounds [1024 x i8], [1024 x i8]* @ga, i32 0, i32 %j
+ store i8 %v, i8* %t, align 1
ret void
}
-; CHECK: memb(r{{[0-9]+}}{{ *}}<<{{ *}}#2{{ *}}+{{ *}}##ga)
-define void @sf5(i32 %i, i8 zeroext %j) nounwind {
+; CHECK-LABEL: test12
+; CHECK: memb(r{{[0-9]+}}<<#2+##ga)
+define void @test12(i32 %i, i8 zeroext %v) nounwind {
entry:
- %mul = shl nsw i32 %i, 2
- %arrayidx = getelementptr inbounds [1024 x i8], [1024 x i8]* @ga, i32 0, i32 %mul
- store i8 %j, i8* %arrayidx, align 1
- ret void
-}
-
-; CHECK: memb(r{{[0-9]+}}{{ *}}<<{{ *}}#2{{ *}}+{{ *}}##gb)
-define void @sf5s(i32 %i, i8 signext %j) nounwind {
-entry:
- %mul = shl nsw i32 %i, 2
- %arrayidx = getelementptr inbounds [1024 x i8], [1024 x i8]* @gb, i32 0, i32 %mul
- store i8 %j, i8* %arrayidx, align 1
+ %j = shl nsw i32 %i, 2
+ %t = getelementptr inbounds [1024 x i8], [1024 x i8]* @ga, i32 0, i32 %j
+ store i8 %v, i8* %t, align 1
ret void
}