| commit | 65d6ea5e68dd5c44f39567f923820d2aef9d41b7 | [log] [tgz] |
|---|---|---|
| author | Alex Bradbury <asb@lowrisc.org> | Wed Mar 21 15:11:02 2018 +0000 |
| committer | Alex Bradbury <asb@lowrisc.org> | Wed Mar 21 15:11:02 2018 +0000 |
| tree | 7955e8dece5ee775ca697279f37bbe287353f947 | |
| parent | 5dd6bd9631935f22711e633a936f489ebd9274c4 [diff] |
[RISCV] Codegen support for RV32F floating point comparison operations This patch also includes extensive tests targeted at select and br+fcmp IR inputs. A sequence of br+fcmp required support for FPR32 registers to be added to RISCVInstrInfo::storeRegToStackSlot and RISCVInstrInfo::loadRegFromStackSlot. llvm-svn: 328104