| =pod |
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| =head1 NAME |
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| llc - LLVM static compiler |
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| =head1 SYNOPSIS |
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| B<llc> [I<options>] [I<filename>] |
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| =head1 DESCRIPTION |
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| The B<llc> command compiles LLVM bitcode into assembly language for a |
| specified architecture. The assembly language output can then be passed through |
| a native assembler and linker to generate a native executable. |
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| The choice of architecture for the output assembly code is automatically |
| determined from the input bitcode file, unless the B<-march> option is used to |
| override the default. |
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| =head1 OPTIONS |
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| If I<filename> is - or omitted, B<llc> reads LLVM bitcode from standard input. |
| Otherwise, it will read LLVM bitcode from I<filename>. |
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| If the B<-o> option is omitted, then B<llc> will send its output to standard |
| output if the input is from standard input. If the B<-o> option specifies -, |
| then the output will also be sent to standard output. |
| |
| If no B<-o> option is specified and an input file other than - is specified, |
| then B<llc> creates the output filename by taking the input filename, |
| removing any existing F<.bc> extension, and adding a F<.s> suffix. |
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| Other B<llc> options are as follows: |
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| =head2 End-user Options |
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| =over |
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| =item B<--help> |
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| Print a summary of command line options. |
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| =item B<-f> |
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| Overwrite output files. By default, B<llc> will refuse to overwrite |
| an output file which already exists. |
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| =item B<-mtriple>=I<target triple> |
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| Override the target triple specified in the input bitcode file with the |
| specified string. |
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| =item B<-march>=I<arch> |
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| Specify the architecture for which to generate assembly, overriding the target |
| encoded in the bitcode file. See the output of B<llc --help> for a list of |
| valid architectures. By default this is inferred from the target triple or |
| autodetected to the current architecture. |
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| =item B<-mcpu>=I<cpuname> |
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| Specify a specific chip in the current architecture to generate code for. |
| By default this is inferred from the target triple and autodetected to |
| the current architecture. For a list of available CPUs, use: |
| B<llvm-as E<lt> /dev/null | llc -march=xyz -mcpu=help> |
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| =item B<-mattr>=I<a1,+a2,-a3,...> |
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| Override or control specific attributes of the target, such as whether SIMD |
| operations are enabled or not. The default set of attributes is set by the |
| current CPU. For a list of available attributes, use: |
| B<llvm-as E<lt> /dev/null | llc -march=xyz -mattr=help> |
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| =item B<--disable-fp-elim> |
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| Disable frame pointer elimination optimization. |
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| =item B<--disable-excess-fp-precision> |
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| Disable optimizations that may produce excess precision for floating point. |
| Note that this option can dramatically slow down code on some systems |
| (e.g. X86). |
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| =item B<--enable-unsafe-fp-math> |
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| Enable optimizations that make unsafe assumptions about IEEE math (e.g. that |
| addition is associative) or may not work for all input ranges. These |
| optimizations allow the code generator to make use of some instructions which |
| would otherwise not be usable (such as fsin on X86). |
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| =item B<--enable-correct-eh-support> |
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| Instruct the B<lowerinvoke> pass to insert code for correct exception handling |
| support. This is expensive and is by default omitted for efficiency. |
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| =item B<--stats> |
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| Print statistics recorded by code-generation passes. |
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| =item B<--time-passes> |
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| Record the amount of time needed for each pass and print a report to standard |
| error. |
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| =item B<--load>=F<dso_path> |
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| Dynamically load F<dso_path> (a path to a dynamically shared object) that |
| implements an LLVM target. This will permit the target name to be used with the |
| B<-march> option so that code can be generated for that target. |
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| =back |
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| =head2 Tuning/Configuration Options |
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| =over |
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| =item B<--print-machineinstrs> |
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| Print generated machine code between compilation phases (useful for debugging). |
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| =item B<--regalloc>=I<allocator> |
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| Specify the register allocator to use. The default I<allocator> is I<local>. |
| Valid register allocators are: |
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| =over |
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| =item I<simple> |
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| Very simple "always spill" register allocator |
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| =item I<local> |
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| Local register allocator |
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| =item I<linearscan> |
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| Linear scan global register allocator |
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| =item I<iterativescan> |
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| Iterative scan global register allocator |
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| =back |
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| =item B<--spiller>=I<spiller> |
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| Specify the spiller to use for register allocators that support it. Currently |
| this option is used only by the linear scan register allocator. The default |
| I<spiller> is I<local>. Valid spillers are: |
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| =over |
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| =item I<simple> |
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| Simple spiller |
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| =item I<local> |
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| Local spiller |
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| =back |
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| =back |
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| =head2 Intel IA-32-specific Options |
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| =over |
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| =item B<--x86-asm-syntax=att|intel> |
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| Specify whether to emit assembly code in AT&T syntax (the default) or intel |
| syntax. |
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| =back |
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| =head1 EXIT STATUS |
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| If B<llc> succeeds, it will exit with 0. Otherwise, if an error occurs, |
| it will exit with a non-zero value. |
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| =head1 SEE ALSO |
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| L<lli|lli> |
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| =head1 AUTHORS |
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| Maintained by the LLVM Team (L<http://llvm.org>). |
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| =cut |