[X86][X87] Tag FCMOV instruction scheduler classes
llvm-svn: 319804
diff --git a/llvm/lib/Target/X86/X86InstrFPStack.td b/llvm/lib/Target/X86/X86InstrFPStack.td
index 2165d75..6788ba5 100644
--- a/llvm/lib/Target/X86/X86InstrFPStack.td
+++ b/llvm/lib/Target/X86/X86InstrFPStack.td
@@ -356,28 +356,31 @@
def FBSTPm : FPI<0xDF, MRM6m, (outs), (ins f80mem:$dst), "fbstp\t$dst">;
// Floating point cmovs.
-class FpIf32CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
- FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32, HasCMov]>;
-class FpIf64CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
- FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64, HasCMov]>;
+class FpIf32CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern,
+ InstrItinClass itin> :
+ FpI_<outs, ins, fp, pattern, itin>, Requires<[FPStackf32, HasCMov]>;
+class FpIf64CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern,
+ InstrItinClass itin> :
+ FpI_<outs, ins, fp, pattern, itin>, Requires<[FPStackf64, HasCMov]>;
multiclass FPCMov<PatLeaf cc> {
def _Fp32 : FpIf32CMov<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2),
CondMovFP,
[(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2,
- cc, EFLAGS))]>;
+ cc, EFLAGS))], IIC_FCMOV>;
def _Fp64 : FpIf64CMov<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2),
CondMovFP,
[(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2,
- cc, EFLAGS))]>;
+ cc, EFLAGS))], IIC_FCMOV>;
def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2),
CondMovFP,
[(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2,
- cc, EFLAGS))]>,
+ cc, EFLAGS))], IIC_FCMOV>,
Requires<[HasCMov]>;
}
let Defs = [FPSW] in {
+let SchedRW = [WriteFAdd] in {
let Uses = [EFLAGS], Constraints = "$src1 = $dst" in {
defm CMOVB : FPCMov<X86_COND_B>;
defm CMOVBE : FPCMov<X86_COND_BE>;
@@ -392,22 +395,23 @@
let Predicates = [HasCMov] in {
// These are not factored because there's no clean way to pass DA/DB.
def CMOVB_F : FPI<0xDA, MRM0r, (outs), (ins RST:$op),
- "fcmovb\t{$op, %st(0)|st(0), $op}">;
+ "fcmovb\t{$op, %st(0)|st(0), $op}", IIC_FCMOV>;
def CMOVBE_F : FPI<0xDA, MRM2r, (outs), (ins RST:$op),
- "fcmovbe\t{$op, %st(0)|st(0), $op}">;
+ "fcmovbe\t{$op, %st(0)|st(0), $op}", IIC_FCMOV>;
def CMOVE_F : FPI<0xDA, MRM1r, (outs), (ins RST:$op),
- "fcmove\t{$op, %st(0)|st(0), $op}">;
+ "fcmove\t{$op, %st(0)|st(0), $op}", IIC_FCMOV>;
def CMOVP_F : FPI<0xDA, MRM3r, (outs), (ins RST:$op),
- "fcmovu\t{$op, %st(0)|st(0), $op}">;
+ "fcmovu\t{$op, %st(0)|st(0), $op}", IIC_FCMOV>;
def CMOVNB_F : FPI<0xDB, MRM0r, (outs), (ins RST:$op),
- "fcmovnb\t{$op, %st(0)|st(0), $op}">;
+ "fcmovnb\t{$op, %st(0)|st(0), $op}", IIC_FCMOV>;
def CMOVNBE_F: FPI<0xDB, MRM2r, (outs), (ins RST:$op),
- "fcmovnbe\t{$op, %st(0)|st(0), $op}">;
+ "fcmovnbe\t{$op, %st(0)|st(0), $op}", IIC_FCMOV>;
def CMOVNE_F : FPI<0xDB, MRM1r, (outs), (ins RST:$op),
- "fcmovne\t{$op, %st(0)|st(0), $op}">;
+ "fcmovne\t{$op, %st(0)|st(0), $op}", IIC_FCMOV>;
def CMOVNP_F : FPI<0xDB, MRM3r, (outs), (ins RST:$op),
- "fcmovnu\t{$op, %st(0)|st(0), $op}">;
+ "fcmovnu\t{$op, %st(0)|st(0), $op}", IIC_FCMOV>;
} // Predicates = [HasCMov]
+} // SchedRW
// Floating point loads & stores.
let canFoldAsLoad = 1 in {
diff --git a/llvm/lib/Target/X86/X86Schedule.td b/llvm/lib/Target/X86/X86Schedule.td
index c43ae0b..f6c3649 100644
--- a/llvm/lib/Target/X86/X86Schedule.td
+++ b/llvm/lib/Target/X86/X86Schedule.td
@@ -447,6 +447,7 @@
def IIC_XADD_LOCK_MEM : InstrItinClass;
def IIC_XADD_LOCK_MEM8 : InstrItinClass;
+def IIC_FCMOV : InstrItinClass;
def IIC_FILD : InstrItinClass;
def IIC_FLD : InstrItinClass;
def IIC_FLD80 : InstrItinClass;
diff --git a/llvm/lib/Target/X86/X86ScheduleAtom.td b/llvm/lib/Target/X86/X86ScheduleAtom.td
index a082199..3142496 100644
--- a/llvm/lib/Target/X86/X86ScheduleAtom.td
+++ b/llvm/lib/Target/X86/X86ScheduleAtom.td
@@ -364,6 +364,7 @@
InstrItinData<IIC_FST80, [InstrStage<5, [Port0, Port1]>] >,
InstrItinData<IIC_FIST, [InstrStage<6, [Port0, Port1]>] >,
+ InstrItinData<IIC_FCMOV, [InstrStage<9, [Port0, Port1]>] >,
InstrItinData<IIC_FLDZ, [InstrStage<1, [Port0, Port1]>] >,
InstrItinData<IIC_FUCOM, [InstrStage<1, [Port1]>] >,
InstrItinData<IIC_FUCOMI, [InstrStage<9, [Port0, Port1]>] >,
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td
index 5ebe8a2..2bae818 100644
--- a/llvm/lib/Target/X86/X86ScheduleZnver1.td
+++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td
@@ -761,7 +761,7 @@
// FLDPI FLDL2E etc.
def : InstRW<[ZnWriteFPU3], (instregex "FLDPI", "FLDL2(T|E)" "FLDL(G|N)2")>;
-def : InstRW<[WriteMicrocoded], (instregex "CMOV(B|BE|P|NB|NBE|NE|NP)_F")>;
+def : InstRW<[WriteMicrocoded], (instregex "CMOV(B|BE|E|P|NB|NBE|NE|NP)_F")>;
// FNSTSW.
// AX.