ARM movw/movt fixups need to mask the high bits.
The fixup value comes in as the whole 32-bit value, so for the lo16 fixup,
the upper bits need to be masked off. Previously we assumed the masking had
already been done and asserted.
rdar://9635991
llvm-svn: 133818
diff --git a/llvm/lib/Target/ARM/ARMAsmBackend.cpp b/llvm/lib/Target/ARM/ARMAsmBackend.cpp
index 79e9897..5e438a9 100644
--- a/llvm/lib/Target/ARM/ARMAsmBackend.cpp
+++ b/llvm/lib/Target/ARM/ARMAsmBackend.cpp
@@ -174,7 +174,8 @@
Value >>= 16;
// Fallthrough
case ARM::fixup_t2_movw_lo16:
- case ARM::fixup_t2_movt_hi16_pcrel:
+ case ARM::fixup_t2_movt_hi16_pcrel: //FIXME: Shouldn't this be shifted like
+ // the other hi16 fixup?
case ARM::fixup_t2_movw_lo16_pcrel: {
unsigned Hi4 = (Value & 0xF000) >> 12;
unsigned i = (Value & 0x800) >> 11;
@@ -184,8 +185,10 @@
// inst{26} = i;
// inst{14-12} = Mid3;
// inst{7-0} = Lo8;
- assert ((((int64_t)Value) >= -0x8000) && (((int64_t)Value) <= 0x7fff) &&
- "Out of range pc-relative fixup value!");
+ // The value comes in as the whole thing, not just the portion required
+ // for this fixup, so we need to mask off the bits not handled by this
+ // portion (lo vs. hi).
+ Value &= 0xffff;
Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
uint64_t swapped = (Value & 0xFFFF0000) >> 16;
swapped |= (Value & 0x0000FFFF) << 16;