commit 666aaf715f110fad2ad8a6b55aaefad234926c22
author Brian Gaeke <gaeke@uiuc.edu> Sat Jan 24 09:23:46 2004 +0000
committer Brian Gaeke <gaeke@uiuc.edu> Sat Jan 24 09:23:46 2004 +0000
tree 65635c2014dc5b0560affdd873c3041011ded3eb
parent 59e3325c264db1bc8af92d19e020a1b8a8a1edec

Fix a couple of places I noticed where "X86" was hard-coded.

llvm-svn: 10974

llvm/utils/TableGen/InstrSelectorEmitter.cpp

diff --git a/llvm/utils/TableGen/InstrSelectorEmitter.cpp b/llvm/utils/TableGen/InstrSelectorEmitter.cpp
index dc5dbf2..5c09393 100644
--- a/llvm/utils/TableGen/InstrSelectorEmitter.cpp
+++ b/llvm/utils/TableGen/InstrSelectorEmitter.cpp
@@ -1023,7 +1023,7 @@
      << "  class " << Target.getName() << "ISel {\n"
      << "    SelectionDAG &DAG;\n"
      << "  public:\n"
-     << "    X86ISel(SelectionDAG &D) : DAG(D) {}\n"
+     << "    " << Target.getName () << "ISel(SelectionDAG &D) : DAG(D) {}\n"
      << "    void generateCode();\n"
      << "  private:\n"
      << "    unsigned makeAnotherReg(const TargetRegisterClass *RC) {\n"
@@ -1060,7 +1060,7 @@
   OS << "  };\n}\n\n";
 
   // Emit the generateCode entry-point...
-  OS << "void X86ISel::generateCode() {\n"
+  OS << "void " << Target.getName () << "ISel::generateCode() {\n"
      << "  SelectionDAGNode *Root = DAG.getRoot();\n"
      << "  assert(Root->getValueType() == MVT::isVoid && "
                                        "\"Root of DAG produces value??\");\n\n"