[X86] Split WriteShuffle/WriteVarShuffle + WriteBlend/WriteVarBlend into XMM and YMM/ZMM scheduler classes
llvm-svn: 331386
diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td
index 999ecd3..ee29d63 100755
--- a/llvm/lib/Target/X86/X86SchedBroadwell.td
+++ b/llvm/lib/Target/X86/X86SchedBroadwell.td
@@ -206,9 +206,13 @@
defm : BWWriteResPair<WriteVecIMul, [BWPort0], 5>; // Vector integer multiply.
defm : BWWriteResPair<WritePMULLD, [BWPort0], 10, [2], 2, 5>; // PMULLD
defm : BWWriteResPair<WriteShuffle, [BWPort5], 1, [1], 1, 5>; // Vector shuffles.
+defm : BWWriteResPair<WriteShuffleY, [BWPort5], 1, [1], 1, 6>; // Vector shuffles (YMM/ZMM).
defm : BWWriteResPair<WriteVarShuffle, [BWPort5], 1, [1], 1, 5>; // Vector variable shuffles.
-defm : BWWriteResPair<WriteBlend, [BWPort5], 1>; // Vector blends.
+defm : BWWriteResPair<WriteVarShuffleY,[BWPort5], 1, [1], 1, 6>; // Vector variable shuffles (YMM/ZMM).
+defm : BWWriteResPair<WriteBlend, [BWPort5], 1, [1], 1, 5>; // Vector blends.
+defm : BWWriteResPair<WriteBlendY, [BWPort5], 1, [1], 1, 6>; // Vector blends (YMM/ZMM).
defm : BWWriteResPair<WriteVarBlend, [BWPort5], 2, [2], 2, 5>; // Vector variable blends.
+defm : BWWriteResPair<WriteVarBlendY, [BWPort5], 2, [2], 2, 6>; // Vector variable blends (YMM/ZMM).
defm : BWWriteResPair<WriteMPSAD, [BWPort0, BWPort5], 7, [1, 2], 3, 5>; // Vector MPSAD.
defm : BWWriteResPair<WritePSADBW, [BWPort0], 5>; // Vector PSADBW.
defm : BWWriteResPair<WritePHMINPOS, [BWPort0], 5>; // Vector PHMINPOS.
@@ -1079,30 +1083,6 @@
"FCOMP32m",
"FCOMP64m")>;
-def BWWriteResGroup75 : SchedWriteRes<[BWPort5,BWPort23]> {
- let Latency = 7;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[BWWriteResGroup75], (instregex "VPACKSSDWYrm",
- "VPACKSSWBYrm",
- "VPACKUSDWYrm",
- "VPACKUSWBYrm",
- "VPALIGNRYrmi",
- "VPBLENDWYrmi",
- "VPSHUFBYrm",
- "VPSHUFDYmi",
- "VPSHUFHWYmi",
- "VPSHUFLWYmi",
- "VPUNPCKHBWYrm",
- "VPUNPCKHDQYrm",
- "VPUNPCKHQDQYrm",
- "VPUNPCKHWDYrm",
- "VPUNPCKLBWYrm",
- "VPUNPCKLDQYrm",
- "VPUNPCKLQDQYrm",
- "VPUNPCKLWDYrm")>;
-
def BWWriteResGroup76 : SchedWriteRes<[BWPort23,BWPort15]> {
let Latency = 7;
let NumMicroOps = 2;
@@ -1293,7 +1273,6 @@
}
def: InstRW<[BWWriteResGroup94], (instregex "VMASKMOVPDYrm",
"VMASKMOVPSYrm",
- "VPBLENDVBYrm",
"VPMASKMOVDYrm",
"VPMASKMOVQYrm")>;
diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td
index 8473c65..aec362f 100644
--- a/llvm/lib/Target/X86/X86SchedHaswell.td
+++ b/llvm/lib/Target/X86/X86SchedHaswell.td
@@ -201,11 +201,15 @@
defm : HWWriteResPair<WriteVecIMul, [HWPort0], 5>;
defm : HWWriteResPair<WritePMULLD, [HWPort0], 10, [2], 2, 6>;
defm : HWWriteResPair<WriteShuffle, [HWPort5], 1, [1], 1, 5>;
-defm : HWWriteResPair<WriteVarShuffle,[HWPort5], 1, [1], 1, 5>;
+defm : HWWriteResPair<WriteShuffleY, [HWPort5], 1, [1], 1, 7>;
+defm : HWWriteResPair<WriteVarShuffle, [HWPort5], 1, [1], 1, 6>;
+defm : HWWriteResPair<WriteVarShuffleY,[HWPort5], 1, [1], 1, 7>;
defm : HWWriteResPair<WriteBlend, [HWPort5], 1, [1], 1, 6>;
+defm : HWWriteResPair<WriteBlendY, [HWPort5], 1, [1], 1, 7>;
defm : HWWriteResPair<WriteShuffle256, [HWPort5], 3, [1], 1, 7>;
defm : HWWriteResPair<WriteVarShuffle256, [HWPort5], 3, [1], 1, 7>;
defm : HWWriteResPair<WriteVarBlend, [HWPort5], 2, [2], 2, 6>;
+defm : HWWriteResPair<WriteVarBlendY, [HWPort5], 2, [2], 2, 7>;
defm : HWWriteResPair<WriteVarVecShift, [HWPort0, HWPort5], 2, [2, 1]>;
defm : HWWriteResPair<WriteMPSAD, [HWPort0, HWPort5], 7, [1, 2], 3, 6>;
defm : HWWriteResPair<WritePSADBW, [HWPort0], 5>;
@@ -880,7 +884,6 @@
"(V?)PACKUSDWrm",
"(V?)PACKUSWBrm",
"(V?)PALIGNRrmi",
- "(V?)PSHUFBrm",
"(V?)PSHUFDmi",
"(V?)PSHUFHWmi",
"(V?)PSHUFLWmi",
@@ -898,27 +901,16 @@
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[HWWriteResGroup13_1], (instregex "VPACKSSDWYrm",
- "VPACKSSWBYrm",
- "VPACKUSDWYrm",
- "VPACKUSWBYrm",
- "VPALIGNRYrmi",
- "VPBLENDWYrmi",
- "VPMOVSXBDYrm",
+def: InstRW<[HWWriteResGroup13_1], (instregex "VPMOVSXBDYrm",
"VPMOVSXBQYrm",
- "VPMOVSXWQYrm",
- "VPSHUFBYrm",
- "VPSHUFDYmi",
- "VPSHUFHWYmi",
- "VPSHUFLWYmi",
- "VPUNPCKHBWYrm",
- "VPUNPCKHDQYrm",
- "VPUNPCKHQDQYrm",
- "VPUNPCKHWDYrm",
- "VPUNPCKLBWYrm",
- "VPUNPCKLDQYrm",
- "VPUNPCKLQDQYrm",
- "VPUNPCKLWDYrm")>;
+ "VPMOVSXWQYrm")>;
+
+def HWWriteResGroup13_2 : SchedWriteRes<[HWPort5,HWPort23]> {
+ let Latency = 6;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
+}
+def: InstRW<[HWWriteResGroup13_2], (instregex "MMX_PSHUFBrm")>;
def HWWriteResGroup14 : SchedWriteRes<[HWPort6,HWPort23]> {
let Latency = 6;
@@ -1244,7 +1236,6 @@
}
def: InstRW<[HWWriteResGroup36_1], (instregex "VMASKMOVPDYrm",
"VMASKMOVPSYrm",
- "VPBLENDVBYrm",
"VPMASKMOVDYrm",
"VPMASKMOVQYrm")>;
diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td
index 0b0817c..8923eb1 100644
--- a/llvm/lib/Target/X86/X86SchedSandyBridge.td
+++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td
@@ -181,9 +181,13 @@
defm : SBWriteResPair<WriteVecIMul, [SBPort0], 5>;
defm : SBWriteResPair<WritePMULLD, [SBPort0], 5, [1], 1, 6>; // TODO this is probably wrong for 256/512-bit for the "generic" model
defm : SBWriteResPair<WriteShuffle, [SBPort5], 1, [1], 1, 5>;
-defm : SBWriteResPair<WriteVarShuffle, [SBPort15], 1, [1], 1, 5>;
+defm : SBWriteResPair<WriteShuffleY, [SBPort5], 1, [1], 1, 7>;
+defm : SBWriteResPair<WriteVarShuffle, [SBPort15], 1, [1], 1, 6>;
+defm : SBWriteResPair<WriteVarShuffleY, [SBPort15], 1, [1], 1, 7>;
defm : SBWriteResPair<WriteBlend, [SBPort15], 1, [1], 1, 6>;
+defm : SBWriteResPair<WriteBlendY, [SBPort15], 1, [1], 1, 7>;
defm : SBWriteResPair<WriteVarBlend, [SBPort15], 2, [2], 2, 6>;
+defm : SBWriteResPair<WriteVarBlendY,[SBPort15], 2, [2], 2, 7>;
defm : SBWriteResPair<WriteMPSAD, [SBPort0, SBPort15], 7, [1,2], 3, 6>;
defm : SBWriteResPair<WritePSADBW, [SBPort0], 5>;
defm : SBWriteResPair<WritePHMINPOS, [SBPort0], 5, [1], 1, 6>;
@@ -884,6 +888,7 @@
}
def: InstRW<[SBWriteResGroup51], (instregex "MMX_PABS(B|D|W)rm",
"MMX_PALIGNRrmi",
+ "MMX_PSHUFBrm",
"MMX_PSIGN(B|D|W)rm")>;
def SBWriteResGroup52 : SchedWriteRes<[SBPort23,SBPort015]> {
@@ -995,7 +1000,6 @@
"(V?)PMOVZXDQrm",
"(V?)PMOVZXWDrm",
"(V?)PMOVZXWQrm",
- "(V?)PSHUFBrm",
"(V?)PSHUFDmi",
"(V?)PSHUFHWmi",
"(V?)PSHUFLWmi",
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
index b76369d..37ad168 100644
--- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
@@ -202,9 +202,13 @@
defm : SKLWriteResPair<WriteVecIMul, [SKLPort0], 5>; // Vector integer multiply.
defm : SKLWriteResPair<WritePMULLD, [SKLPort01], 10, [2], 2, 6>;
defm : SKLWriteResPair<WriteShuffle, [SKLPort5], 1, [1], 1, 5>; // Vector shuffles.
-defm : SKLWriteResPair<WriteVarShuffle, [SKLPort5], 1, [1], 1, 5>; // Vector shuffles.
+defm : SKLWriteResPair<WriteShuffleY, [SKLPort5], 1, [1], 1, 7>; // Vector shuffles (YMM/ZMM).
+defm : SKLWriteResPair<WriteVarShuffle, [SKLPort5], 1, [1], 1, 6>; // Vector shuffles.
+defm : SKLWriteResPair<WriteVarShuffleY, [SKLPort5], 1, [1], 1, 7>; // Vector shuffles (YMM/ZMM).
defm : SKLWriteResPair<WriteBlend, [SKLPort5], 1, [1], 1, 6>; // Vector blends.
+defm : SKLWriteResPair<WriteBlendY, [SKLPort5], 1, [1], 1, 7>; // Vector blends (YMM/ZMM).
defm : SKLWriteResPair<WriteVarBlend, [SKLPort015], 2, [2], 2, 6>; // Vector variable blends.
+defm : SKLWriteResPair<WriteVarBlendY, [SKLPort015], 2, [2], 2, 6>; // Vector variable blends (YMM/ZMM).
defm : SKLWriteResPair<WriteMPSAD, [SKLPort5], 4, [2], 2, 6>; // Vector MPSAD.
defm : SKLWriteResPair<WritePSADBW, [SKLPort5], 3>; // Vector PSADBW.
defm : SKLWriteResPair<WritePHMINPOS, [SKLPort01], 4, [1], 1, 6>; // Vector PHMINPOS.
@@ -1268,7 +1272,6 @@
"(V?)PALIGNRrmi",
"VPBROADCASTBrm",
"VPBROADCASTWrm",
- "(V?)PSHUFBrm",
"(V?)PSHUFDmi",
"(V?)PSHUFHWmi",
"(V?)PSHUFLWmi",
@@ -1281,6 +1284,13 @@
"(V?)PUNPCKLQDQrm",
"(V?)PUNPCKLWDrm")>;
+def SKLWriteResGroup88a : SchedWriteRes<[SKLPort5,SKLPort23]> {
+ let Latency = 6;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
+}
+def: InstRW<[SKLWriteResGroup88a], (instregex "MMX_PSHUFBrm")>;
+
def SKLWriteResGroup89 : SchedWriteRes<[SKLPort5,SKLPort01]> {
let Latency = 7;
let NumMicroOps = 2;
@@ -1496,29 +1506,11 @@
"FCOM64m",
"FCOMP32m",
"FCOMP64m",
- "VPACKSSDWYrm",
- "VPACKSSWBYrm",
- "VPACKUSDWYrm",
- "VPACKUSWBYrm",
- "VPALIGNRYrmi",
- "VPBLENDWYrmi",
"VPBROADCASTBYrm",
"VPBROADCASTWYrm",
"VPMOVSXBDYrm",
"VPMOVSXBQYrm",
- "VPMOVSXWQYrm",
- "VPSHUFBYrm",
- "VPSHUFDYmi",
- "VPSHUFHWYmi",
- "VPSHUFLWYmi",
- "VPUNPCKHBWYrm",
- "VPUNPCKHDQYrm",
- "VPUNPCKHQDQYrm",
- "VPUNPCKHWDYrm",
- "VPUNPCKLBWYrm",
- "VPUNPCKLDQYrm",
- "VPUNPCKLQDQYrm",
- "VPUNPCKLWDYrm")>;
+ "VPMOVSXWQYrm")>;
def SKLWriteResGroup109 : SchedWriteRes<[SKLPort01,SKLPort23]> {
let Latency = 8;
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
index 667b519..4ad0364 100755
--- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
@@ -202,9 +202,13 @@
defm : SKXWriteResPair<WriteVecIMul, [SKXPort0], 5>; // Vector integer multiply.
defm : SKXWriteResPair<WritePMULLD, [SKXPort015], 10, [2], 2, 6>; // Vector integer multiply.
defm : SKXWriteResPair<WriteShuffle, [SKXPort5], 1, [1], 1, 5>; // Vector shuffles.
-defm : SKXWriteResPair<WriteVarShuffle, [SKXPort5], 1, [1], 1, 5>; // Vector variable shuffles.
+defm : SKXWriteResPair<WriteShuffleY, [SKXPort5], 1, [1], 1, 7>; // Vector shuffles (YMM/ZMM).
+defm : SKXWriteResPair<WriteVarShuffle, [SKXPort5], 1, [1], 1, 6>; // Vector variable shuffles.
+defm : SKXWriteResPair<WriteVarShuffleY, [SKXPort5], 1, [1], 1, 7>; // Vector variable shuffles (YMM/ZMM).
defm : SKXWriteResPair<WriteBlend, [SKXPort5], 1, [1], 1, 6>; // Vector blends.
+defm : SKXWriteResPair<WriteBlendY,[SKXPort5], 1, [1], 1, 7>; // Vector blends (YMM/ZMM).
defm : SKXWriteResPair<WriteVarBlend, [SKXPort015], 2, [2], 2, 6>; // Vector variable blends.
+defm : SKXWriteResPair<WriteVarBlendY,[SKXPort015], 2, [2], 2, 6>; // Vector variable blends (YMM/ZMM).
defm : SKXWriteResPair<WriteMPSAD, [SKXPort5], 4, [2], 2, 6>; // Vector MPSAD.
defm : SKXWriteResPair<WritePSADBW, [SKXPort5], 3, [1], 1, 6>; // Vector PSADBW.
defm : SKXWriteResPair<WritePHMINPOS, [SKXPort015], 4, [1], 1, 6>; // Vector PHMINPOS.
@@ -2167,8 +2171,6 @@
"VPBROADCASTBrm",
"VPBROADCASTWZ128m(b?)",
"VPBROADCASTWrm",
- "VPSHUFBZ128rm(b?)",
- "(V?)PSHUFBrm",
"VPSHUFDZ128m(b?)i",
"(V?)PSHUFDmi",
"VPSHUFHWZ128mi(b?)",
@@ -2194,6 +2196,13 @@
"VPUNPCKLWDZ128rm(b?)",
"(V?)PUNPCKLWDrm")>;
+def SKXWriteResGroup92a : SchedWriteRes<[SKXPort5,SKXPort23]> {
+ let Latency = 6;
+ let NumMicroOps = 2;
+ let ResourceCycles = [1,1];
+}
+def: InstRW<[SKXWriteResGroup92a], (instregex "MMX_PSHUFBrm")>;
+
def SKXWriteResGroup93 : SchedWriteRes<[SKXPort5,SKXPort015]> {
let Latency = 7;
let NumMicroOps = 2;
@@ -2629,22 +2638,6 @@
"FCOMP64m",
"MMX_PSADBWirm",
"VFPCLASSSDrm(b?)",
- "VPACKSSDWYrm",
- "VPACKSSDWZ256rm(b?)",
- "VPACKSSDWZrm(b?)",
- "VPACKSSWBYrm",
- "VPACKSSWBZ256rm(b?)",
- "VPACKSSWBZrm(b?)",
- "VPACKUSDWYrm",
- "VPACKUSDWZ256rm(b?)",
- "VPACKUSDWZrm(b?)",
- "VPACKUSWBYrm",
- "VPACKUSWBZ256rm(b?)",
- "VPACKUSWBZrm(b?)",
- "VPALIGNRYrmi",
- "VPALIGNRZ256rmi(b?)",
- "VPALIGNRZrmi(b?)",
- "VPBLENDWYrmi",
"VPBROADCASTBYrm",
"VPBROADCASTBZ256m(b?)",
"VPBROADCASTBZm(b?)",
@@ -2653,47 +2646,7 @@
"VPBROADCASTWZm(b?)",
"VPMOVSXBDYrm",
"VPMOVSXBQYrm",
- "VPMOVSXWQYrm",
- "VPSHUFBYrm",
- "VPSHUFBZ256rm(b?)",
- "VPSHUFBZrm(b?)",
- "VPSHUFDYmi",
- "VPSHUFDZ256m(b?)i",
- "VPSHUFDZm(b?)i",
- "VPSHUFHWYmi",
- "VPSHUFHWZ256mi(b?)",
- "VPSHUFHWZmi(b?)",
- "VPSHUFLWYmi",
- "VPSHUFLWZ256mi(b?)",
- "VPSHUFLWZmi(b?)",
- "VPSLLDQZ256rm(b?)",
- "VPSLLDQZrm(b?)",
- "VPSRLDQZ256rm(b?)",
- "VPSRLDQZrm(b?)",
- "VPUNPCKHBWYrm",
- "VPUNPCKHBWZ256rm(b?)",
- "VPUNPCKHBWZrm(b?)",
- "VPUNPCKHDQYrm",
- "VPUNPCKHDQZ256rm(b?)",
- "VPUNPCKHDQZrm(b?)",
- "VPUNPCKHQDQYrm",
- "VPUNPCKHQDQZ256rm(b?)",
- "VPUNPCKHQDQZrm(b?)",
- "VPUNPCKHWDYrm",
- "VPUNPCKHWDZ256rm(b?)",
- "VPUNPCKHWDZrm(b?)",
- "VPUNPCKLBWYrm",
- "VPUNPCKLBWZ256rm(b?)",
- "VPUNPCKLBWZrm(b?)",
- "VPUNPCKLDQYrm",
- "VPUNPCKLDQZ256rm(b?)",
- "VPUNPCKLDQZrm(b?)",
- "VPUNPCKLQDQYrm",
- "VPUNPCKLQDQZ256rm(b?)",
- "VPUNPCKLQDQZrm(b?)",
- "VPUNPCKLWDYrm",
- "VPUNPCKLWDZ256rm(b?)",
- "VPUNPCKLWDZrm(b?)")>;
+ "VPMOVSXWQYrm")>;
def SKXWriteResGroup120 : SchedWriteRes<[SKXPort01,SKXPort23]> {
let Latency = 8;
diff --git a/llvm/lib/Target/X86/X86Schedule.td b/llvm/lib/Target/X86/X86Schedule.td
index 433f5b1..a264086 100644
--- a/llvm/lib/Target/X86/X86Schedule.td
+++ b/llvm/lib/Target/X86/X86Schedule.td
@@ -139,9 +139,13 @@
defm WriteVecIMul : X86SchedWritePair; // Vector integer multiply.
defm WritePMULLD : X86SchedWritePair; // PMULLD
defm WriteShuffle : X86SchedWritePair; // Vector shuffles.
+defm WriteShuffleY : X86SchedWritePair; // Vector shuffles (YMM/ZMM).
defm WriteVarShuffle : X86SchedWritePair; // Vector variable shuffles.
+defm WriteVarShuffleY : X86SchedWritePair; // Vector variable shuffles (YMM/ZMM).
defm WriteBlend : X86SchedWritePair; // Vector blends.
+defm WriteBlendY : X86SchedWritePair; // Vector blends (YMM/ZMM).
defm WriteVarBlend : X86SchedWritePair; // Vector variable blends.
+defm WriteVarBlendY : X86SchedWritePair; // Vector variable blends (YMM/ZMM).
defm WritePSADBW : X86SchedWritePair; // Vector PSADBW.
defm WriteMPSAD : X86SchedWritePair; // Vector MPSAD.
defm WritePHMINPOS : X86SchedWritePair; // Vector PHMINPOS.
@@ -264,15 +268,15 @@
def SchedWriteShuffle
: X86SchedWriteWidths<WriteShuffle, WriteShuffle,
- WriteShuffle, WriteShuffle>;
+ WriteShuffleY, WriteShuffleY>;
def SchedWriteVarShuffle
: X86SchedWriteWidths<WriteVarShuffle, WriteVarShuffle,
- WriteVarShuffle, WriteVarShuffle>;
+ WriteVarShuffleY, WriteVarShuffleY>;
def SchedWriteBlend
- : X86SchedWriteWidths<WriteBlend, WriteBlend, WriteBlend, WriteBlend>;
+ : X86SchedWriteWidths<WriteBlend, WriteBlend, WriteBlendY, WriteBlendY>;
def SchedWriteVarBlend
: X86SchedWriteWidths<WriteVarBlend, WriteVarBlend,
- WriteVarBlend, WriteVarBlend>;
+ WriteVarBlendY, WriteVarBlendY>;
//===----------------------------------------------------------------------===//
// Generic Processor Scheduler Models.
diff --git a/llvm/lib/Target/X86/X86ScheduleAtom.td b/llvm/lib/Target/X86/X86ScheduleAtom.td
index d022266..3eeeec0 100644
--- a/llvm/lib/Target/X86/X86ScheduleAtom.td
+++ b/llvm/lib/Target/X86/X86ScheduleAtom.td
@@ -261,9 +261,13 @@
defm : AtomWriteResPair<WriteMPSAD, [AtomPort01], [AtomPort0], 1, 1>;
defm : AtomWriteResPair<WritePSADBW, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
defm : AtomWriteResPair<WriteShuffle, [AtomPort0], [AtomPort0], 1, 1>;
+defm : AtomWriteResPair<WriteShuffleY, [AtomPort0], [AtomPort0], 1, 1>;
defm : AtomWriteResPair<WriteVarShuffle, [AtomPort01], [AtomPort01], 4, 5, [4], [5]>;
+defm : AtomWriteResPair<WriteVarShuffleY, [AtomPort01], [AtomPort01], 4, 5, [4], [5]>;
defm : AtomWriteResPair<WriteBlend, [AtomPort0], [AtomPort0]>; // NOTE: Doesn't exist on Atom.
+defm : AtomWriteResPair<WriteBlendY, [AtomPort0], [AtomPort0]>; // NOTE: Doesn't exist on Atom.
defm : AtomWriteResPair<WriteVarBlend, [AtomPort0], [AtomPort0]>; // NOTE: Doesn't exist on Atom.
+defm : AtomWriteResPair<WriteVarBlendY, [AtomPort0], [AtomPort0]>; // NOTE: Doesn't exist on Atom.
defm : AtomWriteResPair<WriteShuffle256, [AtomPort0], [AtomPort0]>; // NOTE: Doesn't exist on Atom.
defm : AtomWriteResPair<WriteVarShuffle256, [AtomPort0], [AtomPort0]>; // NOTE: Doesn't exist on Atom.
defm : AtomWriteResPair<WriteVarVecShift, [AtomPort0], [AtomPort0]>; // NOTE: Doesn't exist on Atom.
diff --git a/llvm/lib/Target/X86/X86ScheduleBtVer2.td b/llvm/lib/Target/X86/X86ScheduleBtVer2.td
index 7d32bc6..9740722 100644
--- a/llvm/lib/Target/X86/X86ScheduleBtVer2.td
+++ b/llvm/lib/Target/X86/X86ScheduleBtVer2.td
@@ -411,9 +411,13 @@
defm : JWriteResFpuPair<WritePSADBW, [JFPU01, JVALU], 2>;
defm : JWriteResFpuPair<WritePHMINPOS, [JFPU0, JVALU], 2>;
defm : JWriteResFpuPair<WriteShuffle, [JFPU01, JVALU], 1>;
+defm : JWriteResFpuPair<WriteShuffleY, [JFPU01, JVALU], 1>;
defm : JWriteResFpuPair<WriteVarShuffle, [JFPU01, JVALU], 2, [1, 4], 3>;
+defm : JWriteResFpuPair<WriteVarShuffleY, [JFPU01, JVALU], 2, [1, 4], 3>;
defm : JWriteResFpuPair<WriteBlend, [JFPU01, JVALU], 1>;
+defm : JWriteResFpuPair<WriteBlendY, [JFPU01, JVALU], 1>;
defm : JWriteResFpuPair<WriteVarBlend, [JFPU01, JVALU], 2, [1, 4], 3>;
+defm : JWriteResFpuPair<WriteVarBlendY, [JFPU01, JVALU], 2, [1, 4], 3>;
defm : JWriteResFpuPair<WriteVecLogic, [JFPU01, JVALU], 1>;
defm : JWriteResFpuPair<WriteVecLogicY, [JFPU01, JVALU], 1>; // NOTE: Doesn't exist on Jaguar.
defm : JWriteResFpuPair<WriteShuffle256, [JFPU01, JVALU], 1>;
diff --git a/llvm/lib/Target/X86/X86ScheduleSLM.td b/llvm/lib/Target/X86/X86ScheduleSLM.td
index c0df1ff..1bc522f 100644
--- a/llvm/lib/Target/X86/X86ScheduleSLM.td
+++ b/llvm/lib/Target/X86/X86ScheduleSLM.td
@@ -171,8 +171,11 @@
//defm : SLMWriteResPair<WritePMULLD, [SLM_FPC_RSV0], 11, [11], 7>;
defm : SLMWriteResPair<WritePMULLD, [SLM_FPC_RSV0], 4>;
defm : SLMWriteResPair<WriteShuffle, [SLM_FPC_RSV0], 1>;
+defm : SLMWriteResPair<WriteShuffleY, [SLM_FPC_RSV0], 1>;
defm : SLMWriteResPair<WriteVarShuffle, [SLM_FPC_RSV0], 1>;
+defm : SLMWriteResPair<WriteVarShuffleY, [SLM_FPC_RSV0], 1>;
defm : SLMWriteResPair<WriteBlend, [SLM_FPC_RSV0], 1>;
+defm : SLMWriteResPair<WriteBlendY, [SLM_FPC_RSV0], 1>;
defm : SLMWriteResPair<WriteMPSAD, [SLM_FPC_RSV0], 7>;
defm : SLMWriteResPair<WritePSADBW, [SLM_FPC_RSV0], 4>;
defm : SLMWriteResPair<WritePHMINPOS, [SLM_FPC_RSV0], 4>;
@@ -290,6 +293,7 @@
def : WriteRes<WriteIMulH, [SLM_FPC_RSV0]>;
defm : SLMWriteResPair<WriteFBlendY, [SLM_FPC_RSV0], 1>;
defm : SLMWriteResPair<WriteVarBlend, [SLM_FPC_RSV0], 1>;
+defm : SLMWriteResPair<WriteVarBlendY,[SLM_FPC_RSV0], 1>;
defm : SLMWriteResPair<WriteFVarBlend, [SLM_FPC_RSV0], 1>;
defm : SLMWriteResPair<WriteFVarBlendY, [SLM_FPC_RSV0], 1>;
defm : SLMWriteResPair<WriteFShuffle256, [SLM_FPC_RSV0], 1>;
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td
index e8230d8..7c70e34 100644
--- a/llvm/lib/Target/X86/X86ScheduleZnver1.td
+++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td
@@ -203,6 +203,7 @@
defm : ZnWriteResFpuPair<WriteFVarBlend, [ZnFPU01], 1>;
defm : ZnWriteResFpuPair<WriteFVarBlendY,[ZnFPU01], 1>;
defm : ZnWriteResFpuPair<WriteVarBlend, [ZnFPU0], 1>;
+defm : ZnWriteResFpuPair<WriteVarBlendY, [ZnFPU0], 1>;
defm : ZnWriteResFpuPair<WriteCvtI2F, [ZnFPU3], 5>;
defm : ZnWriteResFpuPair<WriteCvtF2F, [ZnFPU3], 5>;
defm : ZnWriteResFpuPair<WriteCvtF2I, [ZnFPU3], 5>;
@@ -241,8 +242,11 @@
defm : ZnWriteResFpuPair<WriteVecIMul, [ZnFPU0], 4>;
defm : ZnWriteResFpuPair<WritePMULLD, [ZnFPU0], 4>; // FIXME
defm : ZnWriteResFpuPair<WriteShuffle, [ZnFPU], 1>;
+defm : ZnWriteResFpuPair<WriteShuffleY, [ZnFPU], 1>;
defm : ZnWriteResFpuPair<WriteVarShuffle, [ZnFPU], 1>;
+defm : ZnWriteResFpuPair<WriteVarShuffleY,[ZnFPU], 1>;
defm : ZnWriteResFpuPair<WriteBlend, [ZnFPU01], 1>;
+defm : ZnWriteResFpuPair<WriteBlendY, [ZnFPU01], 1>;
defm : ZnWriteResFpuPair<WriteShuffle256, [ZnFPU], 2>;
defm : ZnWriteResFpuPair<WriteVarShuffle256, [ZnFPU], 2>;
defm : ZnWriteResFpuPair<WritePSADBW, [ZnFPU0], 3>;