6758ecb98cf6a1e2d99f6a53cffe7d4848371cbc - toolchain/llvm-project

commit	6758ecb98cf6a1e2d99f6a53cffe7d4848371cbc	[log] [tgz]
author	Alex Bradbury <asb@lowrisc.org>	Sun Sep 17 14:27:35 2017 +0000
committer	Alex Bradbury <asb@lowrisc.org>	Sun Sep 17 14:27:35 2017 +0000
tree	685021fbf953e218b00c100278cfba3b4113bbfd
parent	06335bbd2ff63e5f67790f26122c76aeae74f822 [diff]

[RISCV] Add support for all RV32I instructions

This patch supports all RV32I instructions as described in the RISC-V manual.
A future patch will add support for pseudoinstructions and other instruction
expansions (e.g. 0-arg fence -> fence iorw, iorw).

Differential Revision: https://reviews.llvm.org/D23566

llvm-svn: 313485

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp[diff]
llvm/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp[diff]
llvm/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.h[diff]
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h[Added - diff]
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp[diff]
llvm/lib/Target/RISCV/RISCVInstrInfo.td[diff]
llvm/test/MC/RISCV/rv32i-invalid.s[diff]
llvm/test/MC/RISCV/rv32i-valid.s[diff]

8 files changed

tree: 685021fbf953e218b00c100278cfba3b4113bbfd

clang/
clang-tools-extra/
compiler-rt/
debuginfo-tests/
libclc/
libcxx/
libcxxabi/
libunwind/
lld/
lldb/
llgo/
llvm/
openmp/
parallel-libs/
polly/