commit 676c16d08856c10e366aa67c56c1c92be737f25a
author Tom Stellard <thomas.stellard@amd.com> Fri Aug 16 01:11:51 2013 +0000
committer Tom Stellard <thomas.stellard@amd.com> Fri Aug 16 01:11:51 2013 +0000
tree d3a98cff8dc24c4af038a0cb7e755242945cb86b
parent ac00f9df7933d244ab4f1078f6c4601dea6bca70

R600: Add IsExport bit to TableGen instruction definitions

Tested-by: Aaron Watry <awatry@gmail.com>
llvm-svn: 188516

llvm/lib/Target/R600/R600Instructions.td

diff --git a/llvm/lib/Target/R600/R600Instructions.td b/llvm/lib/Target/R600/R600Instructions.td
index a67276c..bacedfc 100644
--- a/llvm/lib/Target/R600/R600Instructions.td
+++ b/llvm/lib/Target/R600/R600Instructions.td
@@ -278,6 +278,7 @@
 
   let Inst{31-0} = Word0;
   let Inst{63-32} = Word1;
+  let IsExport = 1;
 
 }
 
@@ -551,6 +552,7 @@
   let elem_size = 3;
   let Inst{31-0} = Word0;
   let Inst{63-32} = Word1;
+  let IsExport = 1;
 }
 
 } // End usesCustomInserter = 1
@@ -564,6 +566,7 @@
   let elem_size = 0;
   let Inst{31-0} = Word0;
   let Inst{63-32} = Word1;
+  let IsExport = 1;
 }
 
 //===----------------------------------------------------------------------===//