commit 676e4db6dc8068e71556326c7a98e0f36d77d7b8
author Andrew Lenharth <andrewl@lenharth.org> Tue May 31 18:37:16 2005 +0000
committer Andrew Lenharth <andrewl@lenharth.org> Tue May 31 18:37:16 2005 +0000
tree 879dec1096a31c5fe72d194433afc72af6bfc153
parent 973d85e660128624491479b7eabc266ff2ae7dc4

switch to the new live in thing

llvm-svn: 22186

llvm/lib/Target/Alpha/AlphaISelPattern.cpp

diff --git a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp
index 59c5998..deed190 100644
--- a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -212,8 +212,8 @@
       case MVT::i64:
         args_int[count] = AddLiveIn(MF, args_int[count], getRegClassFor(VT));
         argt = DAG.getCopyFromReg(args_int[count], VT, DAG.getRoot());
-        //        if (VT != MVT::i64)
-        //          argt = DAG.getNode(ISD::TRUNCATE, VT, argt);
+        if (VT != MVT::i64)
+          argt = DAG.getNode(ISD::TRUNCATE, VT, argt);
         break;
       }
       DAG.setRoot(argt.getValue(1));