commit 67cd347e937b525c8141bfdf6be02f9a1e866554
author Matt Arsenault <Matthew.Arsenault@amd.com> Tue Jun 20 20:38:06 2017 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Tue Jun 20 20:38:06 2017 +0000
tree 5b827a3520cc67bb0fc4596f7e62ae8c27aa039e
parent afdc99333aea79bd3095f5db18d90539f3a1e6ea

AMDGPU: Allow vectorization of packed types

llvm-svn: 305844

llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
index a60b1bb..485e204 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
@@ -75,8 +75,10 @@
     return TTI::PSK_FastHardware;
   }
 
-  unsigned getNumberOfRegisters(bool Vector);
-  unsigned getRegisterBitWidth(bool Vector) const;
+  unsigned getHardwareNumberOfRegisters(bool Vector) const;
+  unsigned getNumberOfRegisters(bool Vector) const;
+  unsigned getRegisterBitWidth(bool Vector) const ;
+  unsigned getMinVectorRegisterBitWidth() const;
   unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const;
 
   bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes,