commit 689f325099bf84da75275aecc1bd01580b78f925
author Matt Arsenault <Matthew.Arsenault@amd.com> Mon Jun 09 16:36:31 2014 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Mon Jun 09 16:36:31 2014 +0000
tree 20ae8880685982a58208e5767ce4bee0bd4519a4
parent 13ccc8f1bc2fbf4da6f22973916f7cca91e44656

R600/SI: Keep 64-bit not on SALU

llvm-svn: 210476

llvm/lib/Target/R600/SIInstrInfo.h

diff --git a/llvm/lib/Target/R600/SIInstrInfo.h b/llvm/lib/Target/R600/SIInstrInfo.h
index 7b31a81..a9b014f 100644
--- a/llvm/lib/Target/R600/SIInstrInfo.h
+++ b/llvm/lib/Target/R600/SIInstrInfo.h
@@ -44,8 +44,11 @@
                          const TargetRegisterClass *RC,
                          const MachineOperand &Op) const;
 
-  void splitScalar64BitOp(SmallVectorImpl<MachineInstr *> & Worklist,
-                          MachineInstr *Inst, unsigned Opcode) const;
+  void splitScalar64BitUnaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
+                               MachineInstr *Inst, unsigned Opcode) const;
+
+  void splitScalar64BitBinaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
+                                MachineInstr *Inst, unsigned Opcode) const;
 
   void addDescImplicitUseDef(const MCInstrDesc &Desc, MachineInstr *MI) const;