[mips] MIPS64R6 compact branch support
MIPS64R6 compact branch support. As the MIPS LLVM backend uses distinct
MachineInstrs for certain 32 and 64 bit instructions (e.g. BEQ & BEQ64) that
map to the same instruction, extend compact branch support for the
corresponding 64bit branches.
Reviewers: dsanders
Differential Revision: https://reviews.llvm.org/D20164
llvm-svn: 276739
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.cpp b/llvm/lib/Target/Mips/MipsInstrInfo.cpp
index 9bbdd7d..de0ceaf 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.cpp
@@ -341,6 +341,22 @@
return Mips::BLTUC;
case Mips::BLTZ:
return Mips::BLTZC;
+ case Mips::BEQ64:
+ if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
+ return 0;
+ return Mips::BEQC64;
+ case Mips::BNE64:
+ if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
+ return 0;
+ return Mips::BNEC64;
+ case Mips::BGTZ64:
+ return Mips::BGTZC64;
+ case Mips::BGEZ64:
+ return Mips::BGEZC64;
+ case Mips::BLTZ64:
+ return Mips::BLTZC64;
+ case Mips::BLEZ64:
+ return Mips::BLEZC64;
// For MIPSR6, the instruction 'jic' can be used for these cases. Some
// tools will accept 'jrc reg' as an alias for 'jic 0, $reg'.
case Mips::JR:
@@ -403,7 +419,7 @@
MachineBasicBlock::iterator I) const {
MachineInstrBuilder MIB;
- // Certain branches have two forms: e.g beq $1, $zero, dst vs beqz $1, dest
+ // Certain branches have two forms: e.g beq $1, $zero, dest vs beqz $1, dest
// Pick the zero form of the branch for readable assembly and for greater
// branch distance in non-microMIPS mode.
// FIXME: Certain atomic sequences on mips64 generate 32bit references to
@@ -429,6 +445,12 @@
case Mips::BLTC:
NewOpc = Mips::BLTZC;
break;
+ case Mips::BEQC64:
+ NewOpc = Mips::BEQZC64;
+ break;
+ case Mips::BNEC64:
+ NewOpc = Mips::BNEZC64;
+ break;
}
}