Hexagon V5 FP Support.
llvm-svn: 156568
diff --git a/llvm/test/CodeGen/Hexagon/convertdptoint.ll b/llvm/test/CodeGen/Hexagon/convertdptoint.ll
new file mode 100644
index 0000000..fa068c4
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/convertdptoint.ll
@@ -0,0 +1,26 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
+; Check that we generate conversion from double precision floating point
+; to 32-bit int value in IEEE complaint mode in V5.
+
+; CHECK: r{{[0-9]+}} = convert_df2w(r{{[0-9]+}}:{{[0-9]+}}):chop
+
+define i32 @main() nounwind {
+entry:
+ %retval = alloca i32, align 4
+ %i = alloca i32, align 4
+ %a = alloca double, align 8
+ %b = alloca double, align 8
+ %c = alloca double, align 8
+ store i32 0, i32* %retval
+ store double 1.540000e+01, double* %a, align 8
+ store double 9.100000e+00, double* %b, align 8
+ %0 = load double* %a, align 8
+ %1 = load double* %b, align 8
+ %add = fadd double %0, %1
+ store double %add, double* %c, align 8
+ %2 = load double* %c, align 8
+ %conv = fptosi double %2 to i32
+ store i32 %conv, i32* %i, align 4
+ %3 = load i32* %i, align 4
+ ret i32 %3
+}
diff --git a/llvm/test/CodeGen/Hexagon/convertdptoll.ll b/llvm/test/CodeGen/Hexagon/convertdptoll.ll
new file mode 100644
index 0000000..1b4dd86
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/convertdptoll.ll
@@ -0,0 +1,27 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
+; Check that we generate conversion from double precision floating point
+; to 64-bit integer value in IEEE complaint mode in V5.
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}} = convert_df2d(r{{[0-9]+}}:{{[0-9]+}}):chop
+
+define i32 @main() nounwind {
+entry:
+ %retval = alloca i32, align 4
+ %i = alloca i64, align 8
+ %a = alloca double, align 8
+ %b = alloca double, align 8
+ %c = alloca double, align 8
+ store i32 0, i32* %retval
+ store double 1.540000e+01, double* %a, align 8
+ store double 9.100000e+00, double* %b, align 8
+ %0 = load double* %a, align 8
+ %1 = load double* %b, align 8
+ %add = fadd double %0, %1
+ store double %add, double* %c, align 8
+ %2 = load double* %c, align 8
+ %conv = fptosi double %2 to i64
+ store i64 %conv, i64* %i, align 8
+ %3 = load i64* %i, align 8
+ %conv1 = trunc i64 %3 to i32
+ ret i32 %conv1
+}
diff --git a/llvm/test/CodeGen/Hexagon/convertsptoint.ll b/llvm/test/CodeGen/Hexagon/convertsptoint.ll
new file mode 100644
index 0000000..b8a9d6c
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/convertsptoint.ll
@@ -0,0 +1,26 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
+; Check that we generate conversion from single precision floating point
+; to 32-bit int value in IEEE complaint mode in V5.
+
+; CHECK: r{{[0-9]+}} = convert_sf2w(r{{[0-9]+}}):chop
+
+define i32 @main() nounwind {
+entry:
+ %retval = alloca i32, align 4
+ %i = alloca i32, align 4
+ %a = alloca float, align 4
+ %b = alloca float, align 4
+ %c = alloca float, align 4
+ store i32 0, i32* %retval
+ store float 0x402ECCCCC0000000, float* %a, align 4
+ store float 0x4022333340000000, float* %b, align 4
+ %0 = load float* %a, align 4
+ %1 = load float* %b, align 4
+ %add = fadd float %0, %1
+ store float %add, float* %c, align 4
+ %2 = load float* %c, align 4
+ %conv = fptosi float %2 to i32
+ store i32 %conv, i32* %i, align 4
+ %3 = load i32* %i, align 4
+ ret i32 %3
+}
diff --git a/llvm/test/CodeGen/Hexagon/convertsptoll.ll b/llvm/test/CodeGen/Hexagon/convertsptoll.ll
new file mode 100644
index 0000000..1c4df94
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/convertsptoll.ll
@@ -0,0 +1,27 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
+; Check that we generate conversion from single precision floating point
+; to 64-bit int value in IEEE complaint mode in V5.
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}} = convert_sf2d(r{{[0-9]+}})
+
+define i32 @main() nounwind {
+entry:
+ %retval = alloca i32, align 4
+ %i = alloca i64, align 8
+ %a = alloca float, align 4
+ %b = alloca float, align 4
+ %c = alloca float, align 4
+ store i32 0, i32* %retval
+ store float 0x402ECCCCC0000000, float* %a, align 4
+ store float 0x4022333340000000, float* %b, align 4
+ %0 = load float* %a, align 4
+ %1 = load float* %b, align 4
+ %add = fadd float %0, %1
+ store float %add, float* %c, align 4
+ %2 = load float* %c, align 4
+ %conv = fptosi float %2 to i64
+ store i64 %conv, i64* %i, align 8
+ %3 = load i64* %i, align 8
+ %conv1 = trunc i64 %3 to i32
+ ret i32 %conv1
+}
diff --git a/llvm/test/CodeGen/Hexagon/dadd.ll b/llvm/test/CodeGen/Hexagon/dadd.ll
new file mode 100644
index 0000000..602978ac
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/dadd.ll
@@ -0,0 +1,19 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
+; Check that we generate double precision floating point add in V5.
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}} = dfadd(r{{[0-9]+}}:{{[0-9]+}}, r{{[0-9]+}}:{{[0-9]+}})
+
+
+define i32 @main() nounwind {
+entry:
+ %a = alloca double, align 8
+ %b = alloca double, align 8
+ %c = alloca double, align 8
+ store double 1.540000e+01, double* %a, align 8
+ store double 9.100000e+00, double* %b, align 8
+ %0 = load double* %a, align 8
+ %1 = load double* %b, align 8
+ %add = fadd double %0, %1
+ store double %add, double* %c, align 8
+ ret i32 0
+}
diff --git a/llvm/test/CodeGen/Hexagon/dmul.ll b/llvm/test/CodeGen/Hexagon/dmul.ll
new file mode 100644
index 0000000..d743773
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/dmul.ll
@@ -0,0 +1,18 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
+; Check that we generate double precision floating point multiply in V5.
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}} = dfmpy(r{{[0-9]+}}:{{[0-9]+}}, r{{[0-9]+}}:{{[0-9]+}})
+
+define i32 @main() nounwind {
+entry:
+ %a = alloca double, align 8
+ %b = alloca double, align 8
+ %c = alloca double, align 8
+ store double 1.540000e+01, double* %a, align 8
+ store double 9.100000e+00, double* %b, align 8
+ %0 = load double* %b, align 8
+ %1 = load double* %a, align 8
+ %mul = fmul double %0, %1
+ store double %mul, double* %c, align 8
+ ret i32 0
+}
diff --git a/llvm/test/CodeGen/Hexagon/doubleconvert-ieee-rnd-near.ll b/llvm/test/CodeGen/Hexagon/doubleconvert-ieee-rnd-near.ll
new file mode 100644
index 0000000..54e7ce3
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/doubleconvert-ieee-rnd-near.ll
@@ -0,0 +1,26 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-hexagon-ieee-rnd-near < %s | FileCheck %s
+; Check that we generate conversion from double precision floating point
+; to 32-bit int value in IEEE rounding to the nearest mode in V5.
+
+; CHECK: r{{[0-9]+}} = convert_df2w(r{{[0-9]+}}:{{[0-9]+}})
+
+define i32 @main() nounwind {
+entry:
+ %retval = alloca i32, align 4
+ %i = alloca i32, align 4
+ %a = alloca double, align 8
+ %b = alloca double, align 8
+ %c = alloca double, align 8
+ store i32 0, i32* %retval
+ store double 1.540000e+01, double* %a, align 8
+ store double 9.100000e+00, double* %b, align 8
+ %0 = load double* %a, align 8
+ %1 = load double* %b, align 8
+ %add = fadd double %0, %1
+ store double %add, double* %c, align 8
+ %2 = load double* %c, align 8
+ %conv = fptosi double %2 to i32
+ store i32 %conv, i32* %i, align 4
+ %3 = load i32* %i, align 4
+ ret i32 %3
+}
diff --git a/llvm/test/CodeGen/Hexagon/dsub.ll b/llvm/test/CodeGen/Hexagon/dsub.ll
new file mode 100644
index 0000000..4f9d39e
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/dsub.ll
@@ -0,0 +1,18 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
+; Check that we generate double precision floating point subtract in V5.
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}} = dfsub(r{{[0-9]+}}:{{[0-9]+}}, r{{[0-9]+}}:{{[0-9]+}})
+
+define i32 @main() nounwind {
+entry:
+ %a = alloca double, align 8
+ %b = alloca double, align 8
+ %c = alloca double, align 8
+ store double 1.540000e+01, double* %a, align 8
+ store double 9.100000e+00, double* %b, align 8
+ %0 = load double* %b, align 8
+ %1 = load double* %a, align 8
+ %sub = fsub double %0, %1
+ store double %sub, double* %c, align 8
+ ret i32 0
+}
diff --git a/llvm/test/CodeGen/Hexagon/fadd.ll b/llvm/test/CodeGen/Hexagon/fadd.ll
new file mode 100644
index 0000000..b95e147
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/fadd.ll
@@ -0,0 +1,18 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
+; Check that we generate sp floating point add in V5.
+
+; CHECK: r{{[0-9]+}} = sfadd(r{{[0-9]+}}, r{{[0-9]+}})
+
+define i32 @main() nounwind {
+entry:
+ %a = alloca float, align 4
+ %b = alloca float, align 4
+ %c = alloca float, align 4
+ store float 0x402ECCCCC0000000, float* %a, align 4
+ store float 0x4022333340000000, float* %b, align 4
+ %0 = load float* %a, align 4
+ %1 = load float* %b, align 4
+ %add = fadd float %0, %1
+ store float %add, float* %c, align 4
+ ret i32 0
+}
diff --git a/llvm/test/CodeGen/Hexagon/fcmp.ll b/llvm/test/CodeGen/Hexagon/fcmp.ll
new file mode 100644
index 0000000..e7b649e
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/fcmp.ll
@@ -0,0 +1,37 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
+; Check that we generate floating point compare in V5
+
+; CHECK: p{{[0-2]+}} = sfcmp.{{.}}
+
+define i32 @foo(float %y) nounwind {
+entry:
+ %retval = alloca i32, align 4
+ %y.addr = alloca float, align 4
+ store float %y, float* %y.addr, align 4
+ %0 = load float* %y.addr, align 4
+ %cmp = fcmp ogt float %0, 0x406AD7EFA0000000
+ br i1 %cmp, label %if.then, label %if.else
+
+if.then: ; preds = %entry
+ store i32 1, i32* %retval
+ br label %return
+
+if.else: ; preds = %entry
+ store i32 2, i32* %retval
+ br label %return
+
+return: ; preds = %if.else, %if.then
+ %1 = load i32* %retval
+ ret i32 %1
+}
+
+define i32 @main() nounwind {
+entry:
+ %retval = alloca i32, align 4
+ %a = alloca float, align 4
+ store i32 0, i32* %retval
+ store float 0x40012E0A00000000, float* %a, align 4
+ %0 = load float* %a, align 4
+ %call = call i32 @foo(float %0)
+ ret i32 %call
+}
diff --git a/llvm/test/CodeGen/Hexagon/floatconvert-ieee-rnd-near.ll b/llvm/test/CodeGen/Hexagon/floatconvert-ieee-rnd-near.ll
new file mode 100644
index 0000000..51acf2e
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/floatconvert-ieee-rnd-near.ll
@@ -0,0 +1,23 @@
+; RUN: true
+; DISABLED: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
+; CHECK: __hexagon_addsf3
+; CHECK: __hexagon_subsf3
+
+define void @foo(float* %acc, float %num, float %num2) nounwind {
+entry:
+ %acc.addr = alloca float*, align 4
+ %num.addr = alloca float, align 4
+ %num2.addr = alloca float, align 4
+ store float* %acc, float** %acc.addr, align 4
+ store float %num, float* %num.addr, align 4
+ store float %num2, float* %num2.addr, align 4
+ %0 = load float** %acc.addr, align 4
+ %1 = load float* %0
+ %2 = load float* %num.addr, align 4
+ %add = fadd float %1, %2
+ %3 = load float* %num2.addr, align 4
+ %sub = fsub float %add, %3
+ %4 = load float** %acc.addr, align 4
+ store float %sub, float* %4
+ ret void
+}
diff --git a/llvm/test/CodeGen/Hexagon/fmul.ll b/llvm/test/CodeGen/Hexagon/fmul.ll
new file mode 100644
index 0000000..4766845
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/fmul.ll
@@ -0,0 +1,19 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
+; Check that we generate single precision floating point multiply in V5.
+
+; CHECK: r{{[0-9]+}} = sfmpy(r{{[0-9]+}}, r{{[0-9]+}})
+
+
+define i32 @main() nounwind {
+entry:
+ %a = alloca float, align 4
+ %b = alloca float, align 4
+ %c = alloca float, align 4
+ store float 0x402ECCCCC0000000, float* %a, align 4
+ store float 0x4022333340000000, float* %b, align 4
+ %0 = load float* %b, align 4
+ %1 = load float* %a, align 4
+ %mul = fmul float %0, %1
+ store float %mul, float* %c, align 4
+ ret i32 0
+}
diff --git a/llvm/test/CodeGen/Hexagon/fsub.ll b/llvm/test/CodeGen/Hexagon/fsub.ll
new file mode 100644
index 0000000..07c866f
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/fsub.ll
@@ -0,0 +1,18 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
+; Check that we generate sp floating point subtract in V5.
+
+; CHECK: r{{[0-9]+}} = sfsub(r{{[0-9]+}}, r{{[0-9]+}})
+
+define i32 @main() nounwind {
+entry:
+ %a = alloca float, align 4
+ %b = alloca float, align 4
+ %c = alloca float, align 4
+ store float 0x402ECCCCC0000000, float* %a, align 4
+ store float 0x4022333340000000, float* %b, align 4
+ %0 = load float* %b, align 4
+ %1 = load float* %a, align 4
+ %sub = fsub float %0, %1
+ store float %sub, float* %c, align 4
+ ret i32 0
+}
diff --git a/llvm/test/CodeGen/Hexagon/opt-fabs.ll b/llvm/test/CodeGen/Hexagon/opt-fabs.ll
new file mode 100644
index 0000000..1cf0dd0
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/opt-fabs.ll
@@ -0,0 +1,15 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
+; Optimize fabsf to clrbit in V5.
+
+; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31)
+
+define float @my_fabsf(float %x) nounwind {
+entry:
+ %x.addr = alloca float, align 4
+ store float %x, float* %x.addr, align 4
+ %0 = load float* %x.addr, align 4
+ %call = call float @fabsf(float %0)
+ ret float %call
+}
+
+declare float @fabsf(float)
diff --git a/llvm/test/CodeGen/Hexagon/opt-fneg.ll b/llvm/test/CodeGen/Hexagon/opt-fneg.ll
new file mode 100644
index 0000000..479b4b6
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/opt-fneg.ll
@@ -0,0 +1,26 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
+; Optimize fneg to togglebit in V5.
+
+define float @foo(float %x) nounwind {
+entry:
+; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #31)
+ %x.addr = alloca float, align 4
+ store float %x, float* %x.addr, align 4
+ %0 = load float* %x.addr, align 4
+ %sub = fsub float -0.000000e+00, %0
+ ret float %sub
+}
+
+define float @bar(float %x) nounwind {
+entry:
+; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #31)
+ %sub = fsub float -0.000000e+00, %x
+ ret float %sub
+}
+
+define float @baz(float %x) nounwind {
+entry:
+; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #31)
+ %conv1 = fmul float %x, -1.000000e+00
+ ret float %conv1
+}