GlobalISel: add generic conditional branch.
Just the basic equivalent to DAG's condbr for now, we'll get to things like
br_cc when we start doing more legalization.
llvm-svn: 277184
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index fb1bfdc..469bd3a 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -104,13 +104,20 @@
bool IRTranslator::translateBr(const Instruction &Inst) {
assert(isa<BranchInst>(Inst) && "Branch expected");
const BranchInst &BrInst = *cast<BranchInst>(&Inst);
- if (BrInst.isUnconditional()) {
- const BasicBlock &BrTgt = *cast<BasicBlock>(BrInst.getOperand(0));
- MachineBasicBlock &TgtBB = getOrCreateBB(BrTgt);
- MIRBuilder.buildBr(TgtBB);
- } else {
- assert(0 && "Not yet implemented");
+
+ unsigned Succ = 0;
+ if (!BrInst.isUnconditional()) {
+ // We want a G_BRCOND to the true BB followed by an unconditional branch.
+ unsigned Tst = getOrCreateVReg(*BrInst.getCondition());
+ const BasicBlock &TrueTgt = *cast<BasicBlock>(BrInst.getSuccessor(Succ++));
+ MachineBasicBlock &TrueBB = getOrCreateBB(TrueTgt);
+ MIRBuilder.buildBrCond(LLT{*BrInst.getCondition()->getType()}, Tst, TrueBB);
}
+
+ const BasicBlock &BrTgt = *cast<BasicBlock>(BrInst.getSuccessor(Succ));
+ MachineBasicBlock &TgtBB = getOrCreateBB(BrTgt);
+ MIRBuilder.buildBr(TgtBB);
+
// Link successors.
MachineBasicBlock &CurBB = MIRBuilder.getMBB();
for (const BasicBlock *Succ : BrInst.successors())
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index 5d61124..426de44 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -95,7 +95,13 @@
return buildInstr(TargetOpcode::COPY).addDef(Res).addUse(Op);
}
-MachineInstrBuilder MachineIRBuilder::buildLoad(LLT VTy, LLT PTy, unsigned Res,
+MachineInstrBuilder MachineIRBuilder::buildBrCond(LLT Ty, unsigned Tst,
+ MachineBasicBlock &Dest) {
+ return buildInstr(TargetOpcode::G_BRCOND, Ty).addUse(Tst).addMBB(&Dest);
+}
+
+
+ MachineInstrBuilder MachineIRBuilder::buildLoad(LLT VTy, LLT PTy, unsigned Res,
unsigned Addr,
MachineMemOperand &MMO) {
return buildInstr(TargetOpcode::G_LOAD, {VTy, PTy})