commit 69ce1c1319634dbf8bc3d6cb4305efea2da0965f
author Diana Picus <diana.picus@linaro.org> Thu Jun 27 08:50:53 2019 +0000
committer Diana Picus <diana.picus@linaro.org> Thu Jun 27 08:50:53 2019 +0000
tree 8c69df9e5994613d7bea68f951efe1cb827fd66c
parent 8479240b0a62efa0481f60db81a60f7638079003

[GlobalISel] Allow multiple VRegs in ArgInfo. NFC

Allow CallLowering::ArgInfo to contain more than one virtual register.
This is useful when passes split aggregates into several virtual
registers, but need to also provide information about the original type
to the call lowering. Used in follow-up patches.

Differential Revision: https://reviews.llvm.org/D63548

llvm-svn: 364509

llvm/lib/Target/X86/X86CallLowering.cpp

diff --git a/llvm/lib/Target/X86/X86CallLowering.cpp b/llvm/lib/Target/X86/X86CallLowering.cpp
index 3f5b007..6403d96 100644
--- a/llvm/lib/Target/X86/X86CallLowering.cpp
+++ b/llvm/lib/Target/X86/X86CallLowering.cpp
@@ -61,6 +61,7 @@
   SmallVector<EVT, 4> SplitVTs;
   SmallVector<uint64_t, 4> Offsets;
   ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, &Offsets, 0);
+  assert(OrigArg.Regs.size() == 1 && "Can't handle multple regs yet");
 
   if (OrigArg.Ty->isVoidTy())
     return true;
@@ -70,7 +71,7 @@
 
   if (NumParts == 1) {
     // replace the original type ( pointer -> GPR ).
-    SplitArgs.emplace_back(OrigArg.Reg, VT.getTypeForEVT(Context),
+    SplitArgs.emplace_back(OrigArg.Regs[0], VT.getTypeForEVT(Context),
                            OrigArg.Flags, OrigArg.IsFixed);
     return true;
   }
@@ -85,7 +86,7 @@
         ArgInfo{MRI.createGenericVirtualRegister(getLLTForType(*PartTy, DL)),
                 PartTy, OrigArg.Flags};
     SplitArgs.push_back(Info);
-    SplitRegs.push_back(Info.Reg);
+    SplitRegs.push_back(Info.Regs[0]);
   }
 
   PerformArgSplit(SplitRegs);
@@ -408,9 +409,10 @@
     if (OrigArg.Flags.isByVal())
       return false;
 
+    assert(OrigArg.Regs.size() == 1 && "Can't handle multple regs yet");
     if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
                            [&](ArrayRef<Register> Regs) {
-                             MIRBuilder.buildUnmerge(Regs, OrigArg.Reg);
+                             MIRBuilder.buildUnmerge(Regs, OrigArg.Regs[0]);
                            }))
       return false;
   }
@@ -450,7 +452,9 @@
   // symmetry with the arguments, the physical register must be an
   // implicit-define of the call instruction.
 
-  if (OrigRet.Reg) {
+  if (!OrigRet.Ty->isVoidTy()) {
+    assert(OrigRet.Regs.size() == 1 && "Can't handle multple regs yet");
+
     SplitArgs.clear();
     SmallVector<Register, 8> NewRegs;
 
@@ -465,7 +469,7 @@
       return false;
 
     if (!NewRegs.empty())
-      MIRBuilder.buildMerge(OrigRet.Reg, NewRegs);
+      MIRBuilder.buildMerge(OrigRet.Regs[0], NewRegs);
   }
 
   CallSeqStart.addImm(Handler.getStackSize())