commit 6bab7ab11e75f675f561162f40c9b28525b4e473
author Matt Arsenault <Matthew.Arsenault@amd.com> Thu Jan 24 23:42:01 2019 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Thu Jan 24 23:42:01 2019 +0000
tree fbf06a1a99471ec1f0800eb95bd49e4b9fa6cdfc
parent 1411ecf08b123e841112839756b0dda502422fe6

RegBankSelect: Fix use after free in r352123

llvm-svn: 352130

llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp

diff --git a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
index 25a979c..c4cd1a3 100644
--- a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
@@ -185,7 +185,7 @@
       unsigned MergeOp = RegTy.isScalar() ?
         TargetOpcode::G_MERGE_VALUES : TargetOpcode::G_BUILD_VECTOR;
 
-      auto &MergeBuilder =
+      auto MergeBuilder =
         MIRBuilder.buildInstrNoInsert(MergeOp)
         .addDef(MO.getReg());