BranchRelaxation: Support expanding unconditional branches
AMDGPU needs to expand unconditional branches in a new
block with an indirect branch.
llvm-svn: 283464
diff --git a/llvm/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll b/llvm/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll
index 15de4dd..8d66df2 100644
--- a/llvm/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll
+++ b/llvm/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll
@@ -4,24 +4,27 @@
; GCN: v_cmp_eq_u32
; GCN: s_and_saveexec_b64
; GCN: s_xor_b64
-; GCN: s_branch BB0_1
+; GCN: ; mask branch [[RET:BB[0-9]+]]
+; GCN: s_branch [[UNREACHABLE:BB[0-9]+_[0-9]+]]
+; GCN: [[RET]]
; GCN: s_or_b64 exec, exec
; GCN: s_endpgm
+; GCN: [[UNREACHABLE]]:
; GCN: ds_write_b32
; GCN: s_waitcnt
define void @lower_control_flow_unreachable_terminator() #0 {
bb:
%tmp15 = tail call i32 @llvm.amdgcn.workitem.id.y()
%tmp63 = icmp eq i32 %tmp15, 32
- br i1 %tmp63, label %bb64, label %bb68
+ br i1 %tmp63, label %unreachable, label %ret
-bb64:
+unreachable:
store volatile i32 0, i32 addrspace(3)* undef, align 4
unreachable
-bb68:
+ret:
ret void
}
@@ -29,21 +32,25 @@
; GCN: v_cmp_eq_u32
; GCN: s_and_saveexec_b64
; GCN: s_xor_b64
-; GCN: s_endpgm
+; GCN: ; mask branch [[UNREACHABLE:BB[0-9]+_[0-9]+]]
-; GCN: s_or_b64 exec, exec
+; GCN-NEXT: ; %ret
+; GCN-NEXT: s_endpgm
+
+; GCN-NEXT: [[UNREACHABLE]]:
+; GCN-NEXT: s_or_b64 exec, exec
; GCN: ds_write_b32
; GCN: s_waitcnt
define void @lower_control_flow_unreachable_terminator_swap_block_order() #0 {
bb:
%tmp15 = tail call i32 @llvm.amdgcn.workitem.id.y()
%tmp63 = icmp eq i32 %tmp15, 32
- br i1 %tmp63, label %bb68, label %bb64
+ br i1 %tmp63, label %ret, label %unreachable
-bb68:
+ret:
ret void
-bb64:
+unreachable:
store volatile i32 0, i32 addrspace(3)* undef, align 4
unreachable
}