commit 6c272a93bbb02f42a2e4386ee1d08d6d25d12de6
author Brian Gaeke <gaeke@uiuc.edu> Mon Apr 19 19:12:12 2004 +0000
committer Brian Gaeke <gaeke@uiuc.edu> Mon Apr 19 19:12:12 2004 +0000
tree 521928f0de8eb5e3e78b31157959c0a9d4551813
parent 627abf14bbe94184aad00163376a0c2c440050ae

Make it legal to request a load or store of %fsr.

llvm-svn: 13073

llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp

diff --git a/llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp b/llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp
index b6da2e6..0f59848 100644
--- a/llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp
+++ b/llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp
@@ -808,6 +808,7 @@
     cpReg2MemMI(mvec, scratchReg, PtrReg, Offset, IntRegType);
     return;
 
+  case SpecialRegType: // used only for %fsr itself.
   case FloatCCRegType: {
     unsigned fsrReg =  getUnifiedRegNum(SparcV9RegInfo::SpecialRegClassID,
                                            SparcV9SpecialRegClass::fsr);
@@ -898,6 +899,7 @@
                                     SparcV9IntCCRegClass::ccr), MachineOperand::Def));
     break;
     
+  case SpecialRegType: // used only for %fsr itself
   case FloatCCRegType: {
     unsigned fsrRegNum =  getUnifiedRegNum(SparcV9RegInfo::SpecialRegClassID,
                                            SparcV9SpecialRegClass::fsr);