[X86] Add CMPSDrr/rm to the scheduler models.
Somehow CMPSSrr/rm was there and the VEX version was there, but this was consistently missing.
llvm-svn: 320289
diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td
index 35f0d99..b1221fc 100644
--- a/llvm/lib/Target/X86/X86SchedHaswell.td
+++ b/llvm/lib/Target/X86/X86SchedHaswell.td
@@ -1586,6 +1586,7 @@
def: InstRW<[HWWriteResGroup12], (instregex "ADDSSrm")>;
def: InstRW<[HWWriteResGroup12], (instregex "BSF(16|32|64)rm")>;
def: InstRW<[HWWriteResGroup12], (instregex "BSR(16|32|64)rm")>;
+def: InstRW<[HWWriteResGroup12], (instregex "CMPSDrm")>;
def: InstRW<[HWWriteResGroup12], (instregex "CMPSSrm")>;
def: InstRW<[HWWriteResGroup12], (instregex "COMISDrm")>;
def: InstRW<[HWWriteResGroup12], (instregex "COMISSrm")>;
@@ -2591,6 +2592,7 @@
def: InstRW<[HWWriteResGroup50], (instregex "BSR(16|32|64)rr")>;
def: InstRW<[HWWriteResGroup50], (instregex "CMPPDrri")>;
def: InstRW<[HWWriteResGroup50], (instregex "CMPPSrri")>;
+def: InstRW<[HWWriteResGroup50], (instregex "CMPSDrr")>;
def: InstRW<[HWWriteResGroup50], (instregex "CMPSSrr")>;
def: InstRW<[HWWriteResGroup50], (instregex "COMISDrr")>;
def: InstRW<[HWWriteResGroup50], (instregex "COMISSrr")>;