Initial patch for supporting Hexagon DSP
llvm-svn: 201665
diff --git a/lldb/include/lldb/Core/ArchSpec.h b/lldb/include/lldb/Core/ArchSpec.h
index 4ec8e06..1ccb385 100644
--- a/lldb/include/lldb/Core/ArchSpec.h
+++ b/lldb/include/lldb/Core/ArchSpec.h
@@ -92,6 +92,10 @@
eCore_x86_64_x86_64,
eCore_x86_64_x86_64h, // Haswell enabled x86_64
+ eCore_hexagon_generic,
+ eCore_hexagon_hexagonv4,
+ eCore_hexagon_hexagonv5,
+
eCore_uknownMach32,
eCore_uknownMach64,
kNumCores,
@@ -103,6 +107,7 @@
kCore_ppc_any,
kCore_ppc64_any,
kCore_x86_32_any,
+ kCore_hexagon_any,
kCore_arm_first = eCore_arm_generic,
kCore_arm_last = eCore_arm_xscale,
@@ -117,7 +122,10 @@
kCore_ppc64_last = eCore_ppc64_ppc970_64,
kCore_x86_32_first = eCore_x86_32_i386,
- kCore_x86_32_last = eCore_x86_32_i486sx
+ kCore_x86_32_last = eCore_x86_32_i486sx,
+
+ kCore_hexagon_first = eCore_hexagon_generic,
+ kCore_hexagon_last = eCore_hexagon_hexagonv5
};
//------------------------------------------------------------------
diff --git a/lldb/source/Core/ArchSpec.cpp b/lldb/source/Core/ArchSpec.cpp
index f4fa224..a93f4bd 100644
--- a/lldb/source/Core/ArchSpec.cpp
+++ b/lldb/source/Core/ArchSpec.cpp
@@ -105,6 +105,10 @@
{ eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64 , ArchSpec::eCore_x86_64_x86_64 , "x86_64" },
{ eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64 , ArchSpec::eCore_x86_64_x86_64h , "x86_64h" },
+ { eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon , ArchSpec::eCore_hexagon_generic, "hexagon" },
+ { eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon , ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4" },
+ { eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon , ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5" },
+
{ eByteOrderLittle, 4, 4, 4 , llvm::Triple::UnknownArch , ArchSpec::eCore_uknownMach32 , "unknown-mach-32" },
{ eByteOrderLittle, 8, 4, 4 , llvm::Triple::UnknownArch , ArchSpec::eCore_uknownMach64 , "unknown-mach-64" }
};
@@ -237,7 +241,8 @@
{ ArchSpec::eCore_arm_generic , llvm::ELF::EM_ARM , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARM
{ ArchSpec::eCore_sparc9_generic , llvm::ELF::EM_SPARCV9, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // SPARC V9
{ ArchSpec::eCore_x86_64_x86_64 , llvm::ELF::EM_X86_64 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // AMD64
- { ArchSpec::eCore_mips64 , llvm::ELF::EM_MIPS , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu } // MIPS
+ { ArchSpec::eCore_mips64 , llvm::ELF::EM_MIPS , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // MIPS
+ { ArchSpec::eCore_hexagon_generic , llvm::ELF::EM_HEXAGON, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu } // HEXAGON
};
static const ArchDefinition g_elf_arch_def = {
@@ -919,6 +924,10 @@
if (core2 == ArchSpec::eCore_arm_armv7)
return true;
}
+
+ case ArchSpec::kCore_hexagon_any:
+ if ((core2 >= ArchSpec::kCore_hexagon_first && core2 <= ArchSpec::kCore_hexagon_last) || (core2 == ArchSpec::kCore_hexagon_any))
+ return true;
break;
case ArchSpec::eCore_arm_armv7m:
diff --git a/lldb/source/Plugins/Platform/Linux/PlatformLinux.cpp b/lldb/source/Plugins/Platform/Linux/PlatformLinux.cpp
index 4e1d949..4b60262 100644
--- a/lldb/source/Plugins/Platform/Linux/PlatformLinux.cpp
+++ b/lldb/source/Plugins/Platform/Linux/PlatformLinux.cpp
@@ -397,6 +397,8 @@
trap_opcode_size = sizeof(g_i386_breakpoint_opcode);
}
break;
+ case ArchSpec::eCore_hexagon_generic:
+ return 0;
}
if (bp_site->SetTrapOpcode(trap_opcode, trap_opcode_size))
diff --git a/lldb/source/Plugins/Platform/Windows/PlatformWindows.cpp b/lldb/source/Plugins/Platform/Windows/PlatformWindows.cpp
index 888a159..6758dc4 100644
--- a/lldb/source/Plugins/Platform/Windows/PlatformWindows.cpp
+++ b/lldb/source/Plugins/Platform/Windows/PlatformWindows.cpp
@@ -291,6 +291,8 @@
}
break;
+ case ArchSpec::eCore_hexagon_generic:
+ return 0;
default:
llvm_unreachable("Unhandled architecture in PlatformWindows::GetSoftwareBreakpointTrapOpcode()");
break;
diff --git a/lldb/source/Target/Thread.cpp b/lldb/source/Target/Thread.cpp
index 72de5b8..39f2699 100644
--- a/lldb/source/Target/Thread.cpp
+++ b/lldb/source/Target/Thread.cpp
@@ -2023,6 +2023,7 @@
case llvm::Triple::arm:
case llvm::Triple::thumb:
case llvm::Triple::mips64:
+ case llvm::Triple::hexagon:
m_unwinder_ap.reset (new UnwindLLDB (*this));
break;