| commit | 6e809de90c0d4284fa41f515c18feb2918f053c6 | [log] [tgz] |
|---|---|---|
| author | Evan Cheng <evan.cheng@apple.com> | Wed Aug 11 06:22:01 2010 +0000 |
| committer | Evan Cheng <evan.cheng@apple.com> | Wed Aug 11 06:22:01 2010 +0000 |
| tree | 40cd122c862dcaee73d541bc1b804cef1f39941a | |
| parent | 8de0a3d8c3cf4f6491412f44e3ed3061b3208dcb [diff] |
- Add subtarget feature -mattr=+db which determine whether an ARM cpu has the memory and synchronization barrier dmb and dsb instructions. - Change instruction names to something more sensible (matching name of actual instructions). - Added tests for memory barrier codegen. llvm-svn: 110785