add basic PPC register-pressure feedback; adjust the vaarg test to match the new register-allocation pattern
llvm-svn: 145065
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 644b20c..b9a6297 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -56,11 +56,8 @@
unsigned Directive = TM->getSubtarget<PPCSubtarget>().getDarwinDirective();
if (Directive == PPC::DIR_440) {
- // Disable the hazard recognizer for now, as it doesn't support
- // bottom-up scheduling.
- //const InstrItineraryData *II = TM->getInstrItineraryData();
- //return new PPCHazardRecognizer440(II, DAG);
- return new ScheduleHazardRecognizer();
+ const InstrItineraryData *II = TM->getInstrItineraryData();
+ return new PPCHazardRecognizer440(II, DAG);
}
else {
// Disable the hazard recognizer for now, as it doesn't support