diff --git a/llvm/test/CodeGen/ARM64/abi.ll b/llvm/test/CodeGen/ARM64/abi.ll
index a7693b6..e2de434 100644
--- a/llvm/test/CodeGen/ARM64/abi.ll
+++ b/llvm/test/CodeGen/ARM64/abi.ll
@@ -77,6 +77,7 @@
 ; CHECK: fixed_4i
 ; CHECK: str [[REG_1:q[0-9]+]], [sp, #16]
 ; FAST: fixed_4i
+; FAST: sub sp, sp, #64
 ; FAST: mov x[[ADDR:[0-9]+]], sp
 ; FAST: str [[REG_1:q[0-9]+]], [x[[ADDR]], #16]
   %0 = load <4 x i32>* %in, align 16
@@ -130,6 +131,7 @@
 ; CHECK: test3
 ; CHECK: str [[REG_1:d[0-9]+]], [sp, #8]
 ; FAST: test3
+; FAST: sub sp, sp, #32
 ; FAST: mov x[[ADDR:[0-9]+]], sp
 ; FAST: str [[REG_1:d[0-9]+]], [x[[ADDR]], #8]
   %0 = load <2 x i32>* %in, align 8
diff --git a/llvm/test/CodeGen/ARM64/abi_align.ll b/llvm/test/CodeGen/ARM64/abi_align.ll
index 61c661e..d8ec395 100644
--- a/llvm/test/CodeGen/ARM64/abi_align.ll
+++ b/llvm/test/CodeGen/ARM64/abi_align.ll
@@ -294,7 +294,7 @@
 ; FAST: sub sp, sp, #96
 ; Space for s1 is allocated at fp-24 = sp+72
 ; Space for s2 is allocated at sp+48
-; FAST: sub x[[A:[0-9]+]], fp, #24
+; FAST: sub x[[A:[0-9]+]], x29, #24
 ; FAST: add x[[A:[0-9]+]], sp, #48
 ; Call memcpy with size = 24 (0x18)
 ; FAST: orr {{x[0-9]+}}, xzr, #0x18
@@ -317,17 +317,17 @@
 define i32 @caller42_stack() #3 {
 entry:
 ; CHECK: caller42_stack
-; CHECK: mov fp, sp
+; CHECK: mov x29, sp
 ; CHECK: sub sp, sp, #96
-; CHECK: stur {{x[0-9]+}}, [fp, #-16]
-; CHECK: stur {{q[0-9]+}}, [fp, #-32]
+; CHECK: stur {{x[0-9]+}}, [x29, #-16]
+; CHECK: stur {{q[0-9]+}}, [x29, #-32]
 ; CHECK: str {{x[0-9]+}}, [sp, #48]
 ; CHECK: str {{q[0-9]+}}, [sp, #32]
-; Space for s1 is allocated at fp-32 = sp+64
+; Space for s1 is allocated at x29-32 = sp+64
 ; Space for s2 is allocated at sp+32
 ; CHECK: add x[[B:[0-9]+]], sp, #32
 ; CHECK: str x[[B]], [sp, #16]
-; CHECK: sub x[[A:[0-9]+]], fp, #32
+; CHECK: sub x[[A:[0-9]+]], x29, #32
 ; Address of s1 is passed on stack at sp+8
 ; CHECK: str x[[A]], [sp, #8]
 ; CHECK: movz w[[C:[0-9]+]], #9
@@ -336,8 +336,8 @@
 ; FAST: caller42_stack
 ; Space for s1 is allocated at fp-24
 ; Space for s2 is allocated at fp-48
-; FAST: sub x[[A:[0-9]+]], fp, #24
-; FAST: sub x[[B:[0-9]+]], fp, #48
+; FAST: sub x[[A:[0-9]+]], x29, #24
+; FAST: sub x[[B:[0-9]+]], x29, #48
 ; Call memcpy with size = 24 (0x18)
 ; FAST: orr {{x[0-9]+}}, xzr, #0x18
 ; FAST: str {{w[0-9]+}}, [sp]
@@ -399,7 +399,7 @@
 ; Space for s2 is allocated at sp
 
 ; FAST: caller43
-; FAST: mov fp, sp
+; FAST: mov x29, sp
 ; Space for s1 is allocated at sp+32
 ; Space for s2 is allocated at sp
 ; FAST: add x1, sp, #32
@@ -429,17 +429,17 @@
 define i32 @caller43_stack() #3 {
 entry:
 ; CHECK: caller43_stack
-; CHECK: mov fp, sp
+; CHECK: mov x29, sp
 ; CHECK: sub sp, sp, #96
-; CHECK: stur {{q[0-9]+}}, [fp, #-16]
-; CHECK: stur {{q[0-9]+}}, [fp, #-32]
+; CHECK: stur {{q[0-9]+}}, [x29, #-16]
+; CHECK: stur {{q[0-9]+}}, [x29, #-32]
 ; CHECK: str {{q[0-9]+}}, [sp, #48]
 ; CHECK: str {{q[0-9]+}}, [sp, #32]
-; Space for s1 is allocated at fp-32 = sp+64
+; Space for s1 is allocated at x29-32 = sp+64
 ; Space for s2 is allocated at sp+32
 ; CHECK: add x[[B:[0-9]+]], sp, #32
 ; CHECK: str x[[B]], [sp, #16]
-; CHECK: sub x[[A:[0-9]+]], fp, #32
+; CHECK: sub x[[A:[0-9]+]], x29, #32
 ; Address of s1 is passed on stack at sp+8
 ; CHECK: str x[[A]], [sp, #8]
 ; CHECK: movz w[[C:[0-9]+]], #9
@@ -449,12 +449,12 @@
 ; FAST: sub sp, sp, #96
 ; Space for s1 is allocated at fp-32 = sp+64
 ; Space for s2 is allocated at sp+32
-; FAST: sub x[[A:[0-9]+]], fp, #32
+; FAST: sub x[[A:[0-9]+]], x29, #32
 ; FAST: add x[[B:[0-9]+]], sp, #32
-; FAST: stur {{x[0-9]+}}, [fp, #-32]
-; FAST: stur {{x[0-9]+}}, [fp, #-24]
-; FAST: stur {{x[0-9]+}}, [fp, #-16]
-; FAST: stur {{x[0-9]+}}, [fp, #-8]
+; FAST: stur {{x[0-9]+}}, [x29, #-32]
+; FAST: stur {{x[0-9]+}}, [x29, #-24]
+; FAST: stur {{x[0-9]+}}, [x29, #-16]
+; FAST: stur {{x[0-9]+}}, [x29, #-8]
 ; FAST: str {{x[0-9]+}}, [sp, #32]
 ; FAST: str {{x[0-9]+}}, [sp, #40]
 ; FAST: str {{x[0-9]+}}, [sp, #48]
@@ -487,6 +487,7 @@
 ; CHECK: str {{w[0-9]+}}, [sp, #16]
 ; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp]
 ; FAST: i128_split
+; FAST: sub sp, sp, #48
 ; FAST: mov x[[ADDR:[0-9]+]], sp
 ; FAST: str {{w[0-9]+}}, [x[[ADDR]], #16]
 ; FAST: stp {{x[0-9]+}}, {{x[0-9]+}}, [x[[ADDR]]]
diff --git a/llvm/test/CodeGen/ARM64/fast-isel-alloca.ll b/llvm/test/CodeGen/ARM64/fast-isel-alloca.ll
index 8bbee16..1706e9e 100644
--- a/llvm/test/CodeGen/ARM64/fast-isel-alloca.ll
+++ b/llvm/test/CodeGen/ARM64/fast-isel-alloca.ll
@@ -14,6 +14,7 @@
 define void @main() nounwind {
 entry:
 ; CHECK: main
+; CHECK: mov x29, sp
 ; CHECK: mov x[[REG:[0-9]+]], sp
 ; CHECK-NEXT: orr x[[REG1:[0-9]+]], xzr, #0x8
 ; CHECK-NEXT: add x0, x[[REG]], x[[REG1]]
diff --git a/llvm/test/CodeGen/ARM64/fast-isel-call.ll b/llvm/test/CodeGen/ARM64/fast-isel-call.ll
index be0ca68..637ce28 100644
--- a/llvm/test/CodeGen/ARM64/fast-isel-call.ll
+++ b/llvm/test/CodeGen/ARM64/fast-isel-call.ll
@@ -24,8 +24,8 @@
 define i32 @foo1(i32 %a) nounwind {
 entry:
 ; CHECK: foo1
-; CHECK: stur w0, [fp, #-4]
-; CHECK-NEXT: ldur w0, [fp, #-4]
+; CHECK: stur w0, [x29, #-4]
+; CHECK-NEXT: ldur w0, [x29, #-4]
 ; CHECK-NEXT: bl _call1
   %a.addr = alloca i32, align 4
   store i32 %a, i32* %a.addr, align 4
diff --git a/llvm/test/CodeGen/ARM64/frameaddr.ll b/llvm/test/CodeGen/ARM64/frameaddr.ll
index d0635ad..e7cff60 100644
--- a/llvm/test/CodeGen/ARM64/frameaddr.ll
+++ b/llvm/test/CodeGen/ARM64/frameaddr.ll
@@ -3,10 +3,10 @@
 define i8* @t() nounwind {
 entry:
 ; CHECK-LABEL: t:
-; CHECK: stp fp, lr, [sp, #-16]!
-; CHECK: mov fp, sp
-; CHECK: mov x0, fp
-; CHECK: ldp fp, lr, [sp], #16
+; CHECK: stp x29, lr, [sp, #-16]!
+; CHECK: mov x29, sp
+; CHECK: mov x0, x29
+; CHECK: ldp x29, lr, [sp], #16
 ; CHECK: ret
 	%0 = call i8* @llvm.frameaddress(i32 0)
         ret i8* %0
diff --git a/llvm/test/CodeGen/ARM64/hello.ll b/llvm/test/CodeGen/ARM64/hello.ll
index f870fff..06efacb 100644
--- a/llvm/test/CodeGen/ARM64/hello.ll
+++ b/llvm/test/CodeGen/ARM64/hello.ll
@@ -2,27 +2,27 @@
 ; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s --check-prefix=CHECK-LINUX
 
 ; CHECK-LABEL: main:
-; CHECK:	stp	fp, lr, [sp, #-16]!
-; CHECK-NEXT:	mov	fp, sp
+; CHECK:	stp	x29, lr, [sp, #-16]!
+; CHECK-NEXT:	mov	x29, sp
 ; CHECK-NEXT:	sub	sp, sp, #16
-; CHECK-NEXT:	stur	wzr, [fp, #-4]
+; CHECK-NEXT:	stur	wzr, [x29, #-4]
 ; CHECK:	adrp	x0, L_.str@PAGE
 ; CHECK:	add	x0, x0, L_.str@PAGEOFF
 ; CHECK-NEXT:	bl	_puts
-; CHECK-NEXT:	mov	sp, fp
-; CHECK-NEXT:	ldp	fp, lr, [sp], #16
+; CHECK-NEXT:	mov	sp, x29
+; CHECK-NEXT:	ldp	x29, lr, [sp], #16
 ; CHECK-NEXT:	ret
 
 ; CHECK-LINUX-LABEL: main:
-; CHECK-LINUX:	stp	fp, lr, [sp, #-16]!
-; CHECK-LINUX-NEXT:	mov	fp, sp
+; CHECK-LINUX:	stp	x29, lr, [sp, #-16]!
+; CHECK-LINUX-NEXT:	mov	x29, sp
 ; CHECK-LINUX-NEXT:	sub	sp, sp, #16
-; CHECK-LINUX-NEXT:	stur	wzr, [fp, #-4]
+; CHECK-LINUX-NEXT:	stur	wzr, [x29, #-4]
 ; CHECK-LINUX:	adrp	x0, .L.str
 ; CHECK-LINUX:	add	x0, x0, :lo12:.L.str
 ; CHECK-LINUX-NEXT:	bl	puts
-; CHECK-LINUX-NEXT:	mov	sp, fp
-; CHECK-LINUX-NEXT:	ldp	fp, lr, [sp], #16
+; CHECK-LINUX-NEXT:	mov	sp, x29
+; CHECK-LINUX-NEXT:	ldp	x29, lr, [sp], #16
 ; CHECK-LINUX-NEXT:	ret
 
 @.str = private unnamed_addr constant [7 x i8] c"hello\0A\00"
diff --git a/llvm/test/CodeGen/ARM64/patchpoint.ll b/llvm/test/CodeGen/ARM64/patchpoint.ll
index 993e3eb..c9f63d9 100644
--- a/llvm/test/CodeGen/ARM64/patchpoint.ll
+++ b/llvm/test/CodeGen/ARM64/patchpoint.ll
@@ -25,10 +25,10 @@
 ; as a leaf function.
 ;
 ; CHECK-LABEL: caller_meta_leaf
-; CHECK:       mov fp, sp
+; CHECK:       mov x29, sp
 ; CHECK-NEXT:  sub sp, sp, #32
 ; CHECK:       Ltmp
-; CHECK:       mov sp, fp
+; CHECK:       mov sp, x29
 ; CHECK:       ret
 
 define void @caller_meta_leaf() {
diff --git a/llvm/test/CodeGen/ARM64/returnaddr.ll b/llvm/test/CodeGen/ARM64/returnaddr.ll
index e06ce90..76c8e18 100644
--- a/llvm/test/CodeGen/ARM64/returnaddr.ll
+++ b/llvm/test/CodeGen/ARM64/returnaddr.ll
@@ -12,12 +12,12 @@
 define i8* @rt2() nounwind readnone {
 entry:
 ; CHECK-LABEL: rt2:
-; CHECK: stp fp, lr, [sp, #-16]!
-; CHECK: mov fp, sp
-; CHECK: ldr x[[REG:[0-9]+]], [fp]
+; CHECK: stp x29, lr, [sp, #-16]!
+; CHECK: mov x29, sp
+; CHECK: ldr x[[REG:[0-9]+]], [x29]
 ; CHECK: ldr x[[REG2:[0-9]+]], [x[[REG]]]
 ; CHECK: ldr x0, [x[[REG2]], #8]
-; CHECK: ldp fp, lr, [sp], #16
+; CHECK: ldp x29, lr, [sp], #16
 ; CHECK: ret
   %0 = tail call i8* @llvm.returnaddress(i32 2)
   ret i8* %0