6f2a526101bfef214aef8cae8dba4a9cce55b6fa - toolchain/llvm-project

commit	6f2a526101bfef214aef8cae8dba4a9cce55b6fa	[log] [tgz]
author	Matt Arsenault <Matthew.Arsenault@amd.com>	Sun Jul 27 17:46:40 2014 +0000
committer	Matt Arsenault <Matthew.Arsenault@amd.com>	Sun Jul 27 17:46:40 2014 +0000
tree	7fdf854c43b57af4354e0d48aec858b4e72b18be
parent	b3cd5a1037d71e33b2519fcaf66e2978679f3c22 [diff]

Add alignment value to allowsUnalignedMemoryAccess

Rename to allowsMisalignedMemoryAccess.

On R600, 8 and 16 byte accesses are mostly OK with 4-byte alignment,
and don't need to be split into multiple accesses. Vector loads with
an alignment of the element type are not uncommon in OpenCL code.

llvm-svn: 214055

llvm/include/llvm/Target/TargetLowering.h[diff]
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp[diff]
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp[diff]
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp[diff]
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp[diff]
llvm/lib/Target/AArch64/AArch64ISelLowering.h[diff]
llvm/lib/Target/ARM/ARMISelLowering.cpp[diff]
llvm/lib/Target/ARM/ARMISelLowering.h[diff]
llvm/lib/Target/ARM/ARMSubtarget.h[diff]
llvm/lib/Target/Mips/Mips16ISelLowering.cpp[diff]
llvm/lib/Target/Mips/Mips16ISelLowering.h[diff]
llvm/lib/Target/Mips/MipsSEISelLowering.cpp[diff]
llvm/lib/Target/Mips/MipsSEISelLowering.h[diff]
llvm/lib/Target/PowerPC/PPCISelLowering.cpp[diff]
llvm/lib/Target/PowerPC/PPCISelLowering.h[diff]
llvm/lib/Target/R600/SIISelLowering.cpp[diff]
llvm/lib/Target/R600/SIISelLowering.h[diff]
llvm/lib/Target/SystemZ/SystemZISelLowering.cpp[diff]
llvm/lib/Target/SystemZ/SystemZISelLowering.h[diff]
llvm/lib/Target/X86/X86ISelLowering.cpp[diff]
llvm/lib/Target/X86/X86ISelLowering.h[diff]
llvm/lib/Target/XCore/XCoreISelLowering.cpp[diff]
llvm/test/CodeGen/R600/unaligned-load-store.ll[diff]

23 files changed

tree: 7fdf854c43b57af4354e0d48aec858b4e72b18be

clang/
clang-tools-extra/
compiler-rt/
debuginfo-tests/
libclc/
libcxx/
libcxxabi/
lld/
lldb/
llvm/
openmp/
polly/