[Hexagon] Use isMetaInstruction instead of isDebugValue
llvm-svn: 310601
diff --git a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
index 6b4f5342..86c877e 100644
--- a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
@@ -253,7 +253,8 @@
const TargetRegisterInfo *TRI) {
return (UseReg && (MI.modifiesRegister(UseReg, TRI))) ||
MI.modifiesRegister(DestReg, TRI) || MI.readsRegister(DestReg, TRI) ||
- MI.hasUnmodeledSideEffects() || MI.isInlineAsm() || MI.isDebugValue();
+ MI.hasUnmodeledSideEffects() || MI.isInlineAsm() ||
+ MI.isMetaInstruction();
}
static unsigned UseReg(const MachineOperand& MO) {
diff --git a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
index fdf57a8..b314e06 100644
--- a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
@@ -539,7 +539,7 @@
return 0u;
unsigned T = std::count_if(B->begin(), B->getFirstTerminator(),
[](const MachineInstr &MI) {
- return !MI.isDebugValue();
+ return !MI.isMetaInstruction();
});
if (T < HEXAGON_PACKET_SIZE)
Spare += HEXAGON_PACKET_SIZE-T;
diff --git a/llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp b/llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp
index 23d4e26..501ac2c 100644
--- a/llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp
@@ -138,7 +138,7 @@
MachineBasicBlock::iterator MIE = MBB.end();
while (MII != MIE) {
InstOffset += HII->getSize(*MII);
- if (MII->isDebugValue()) {
+ if (MII->isMetaInstruction()) {
++MII;
continue;
}