Re-apply "r351584: "GlobalISel: Verify g_zextload and g_sextload""
I reverted it originally due to a bot failing. The underlying bug has been fixed
as of r352311.
llvm-svn: 352312
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index ad7825b..879a3d3 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1002,11 +1002,24 @@
}
case TargetOpcode::G_LOAD:
case TargetOpcode::G_STORE:
+ case TargetOpcode::G_ZEXTLOAD:
+ case TargetOpcode::G_SEXTLOAD:
// Generic loads and stores must have a single MachineMemOperand
// describing that access.
- if (!MI->hasOneMemOperand())
+ if (!MI->hasOneMemOperand()) {
report("Generic instruction accessing memory must have one mem operand",
MI);
+ } else {
+ if (MI->getOpcode() == TargetOpcode::G_ZEXTLOAD ||
+ MI->getOpcode() == TargetOpcode::G_SEXTLOAD) {
+ const MachineMemOperand &MMO = **MI->memoperands_begin();
+ LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
+ if (MMO.getSize() * 8 >= DstTy.getSizeInBits()) {
+ report("Generic extload must have a narrower memory type", MI);
+ }
+ }
+ }
+
break;
case TargetOpcode::G_PHI: {
LLT DstTy = MRI->getType(MI->getOperand(0).getReg());