[AMDGPU] For OS type AMDPAL, fixed scratch on compute shader
Summary:
For OS type AMDPAL, the scratch descriptor is loaded from offset 0 of
the GIT, whose 32 bit pointer is in s0 (s8 for gfx9 merged shaders).
This commit fixes that to use offset 0x10 instead of offset 0 for a
compute shader, per the PAL ABI spec.
V2: Ensure s0 (s8 for gfx9 merged shader) is marked live-in when loading
scratch descriptor from GIT.
Reviewers: kzhuravl, nhaehnle, timcorringham
Subscribers: kzhuravl, wdng, yaxunl, t-tye, llvm-commits, dstuttard, nhaehnle, arsenm
Differential Revision: https://reviews.llvm.org/D44468
Change-Id: I93dffa647758e37f613bb5e0dfca840d82e6d26f
llvm-svn: 329690
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal.ll b/llvm/test/CodeGen/AMDGPU/amdpal.ll
index c8f37fb..8d4c09c 100644
--- a/llvm/test/CodeGen/AMDGPU/amdpal.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdpal.ll
@@ -52,7 +52,36 @@
ret void
}
+; Check code sequence for amdpal use of scratch for alloca in a compute shader.
+; The scratch descriptor is loaded from offset 0x10 of the GIT, rather than offset
+; 0 in a graphics shader.
+
+; PAL-LABEL: {{^}}scratch2_cs:
+; PAL: s_movk_i32 s{{[0-9]+}}, 0x1234
+; PAL: s_mov_b32 s[[GITPTR:[0-9]+]], s0
+; PAL: s_load_dwordx4 s{{\[}}[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s{{\[}}[[GITPTR]]:{{[0-9]+\]}}, 0x10
+; PAL: buffer_store{{.*}}, s{{\[}}[[SCRATCHDESC]]:
+
+define amdgpu_cs void @scratch2_cs(i32 inreg, i32 inreg, i32 inreg, <3 x i32> inreg, i32 inreg, <3 x i32> %coord, <2 x i32> %in, i32 %extra, i32 %idx) #0 {
+entry:
+ %v = alloca [3 x i32], addrspace(5)
+ %v0 = getelementptr [3 x i32], [3 x i32] addrspace(5)* %v, i32 0, i32 0
+ %v1 = getelementptr [3 x i32], [3 x i32] addrspace(5)* %v, i32 0, i32 1
+ store i32 %extra, i32 addrspace(5)* %v0
+ %v1a = bitcast i32 addrspace(5)* %v1 to [2 x i32] addrspace(5)*
+ %vv = bitcast [2 x i32] addrspace(5)* %v1a to <2 x i32> addrspace(5)*
+ store <2 x i32> %in, <2 x i32> addrspace(5)* %vv
+ %e = getelementptr [2 x i32], [2 x i32] addrspace(5)* %v1a, i32 0, i32 %idx
+ %x = load i32, i32 addrspace(5)* %e
+ %xf = bitcast i32 %x to float
+ call void @llvm.amdgcn.buffer.store.f32(float %xf, <4 x i32> undef, i32 0, i32 0, i1 0, i1 0)
+ ret void
+}
+
attributes #0 = { nounwind "amdgpu-git-ptr-high"="0x1234" }
+declare void @llvm.amdgcn.buffer.store.f32(float, <4 x i32>, i32, i32, i1, i1)
+
+
; Check we have CS_NUM_USED_VGPRS in PAL metadata.
; PAL: .amd_amdgpu_pal_metadata {{.*}},0x10000027,