Add backend name to Target to enable runtime info to be fed back into TableGen
Summary:
Make it possible to feed runtime information back to tablegen to enable
profile-guided tablegen-eration, detection of untested tablegen definitions, etc.
Being a cross-compiler by nature, LLVM will potentially collect data for multiple
architectures (e.g. when running 'ninja check'). We therefore need a way for
TableGen to figure out what data applies to the backend it is generating at the
time. This patch achieves that by including the name of the 'def X : Target ...'
for the backend in the TargetRegistry.
Reviewers: qcolombet
Reviewed By: qcolombet
Subscribers: jholewinski, arsenm, jyknight, aditya_nandakumar, sdardis, nemanjai, ab, nhaehnle, t.p.northover, javed.absar, qcolombet, llvm-commits, fedor.sergeev
Differential Revision: https://reviews.llvm.org/D39742
llvm-svn: 318352
diff --git a/llvm/lib/Support/TargetRegistry.cpp b/llvm/lib/Support/TargetRegistry.cpp
index b5c2832..ed999fc 100644
--- a/llvm/lib/Support/TargetRegistry.cpp
+++ b/llvm/lib/Support/TargetRegistry.cpp
@@ -86,9 +86,9 @@
return &*I;
}
-void TargetRegistry::RegisterTarget(Target &T,
- const char *Name,
+void TargetRegistry::RegisterTarget(Target &T, const char *Name,
const char *ShortDesc,
+ const char *BackendName,
Target::ArchMatchFnTy ArchMatchFn,
bool HasJIT) {
assert(Name && ShortDesc && ArchMatchFn &&
@@ -105,6 +105,7 @@
T.Name = Name;
T.ShortDesc = ShortDesc;
+ T.BackendName = BackendName;
T.ArchMatchFn = ArchMatchFn;
T.HasJIT = HasJIT;
}
diff --git a/llvm/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp b/llvm/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp
index 7ac9a5a..8fb1615 100644
--- a/llvm/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp
+++ b/llvm/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp
@@ -29,11 +29,11 @@
// Now register the "arm64" name for use with "-march". We don't want it to
// take possession of the Triple::aarch64 tag though.
TargetRegistry::RegisterTarget(getTheARM64Target(), "arm64",
- "ARM64 (little endian)",
+ "ARM64 (little endian)", "AArch64",
[](Triple::ArchType) { return false; }, true);
RegisterTarget<Triple::aarch64, /*HasJIT=*/true> Z(
- getTheAArch64leTarget(), "aarch64", "AArch64 (little endian)");
+ getTheAArch64leTarget(), "aarch64", "AArch64 (little endian)", "AArch64");
RegisterTarget<Triple::aarch64_be, /*HasJIT=*/true> W(
- getTheAArch64beTarget(), "aarch64_be", "AArch64 (big endian)");
+ getTheAArch64beTarget(), "aarch64_be", "AArch64 (big endian)", "AArch64");
}
diff --git a/llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp b/llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp
index 92fb762..f61e2e4 100644
--- a/llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp
@@ -31,7 +31,7 @@
/// \brief Extern function to initialize the targets for the AMDGPU backend
extern "C" void LLVMInitializeAMDGPUTargetInfo() {
RegisterTarget<Triple::r600, false> R600(getTheAMDGPUTarget(), "r600",
- "AMD GPUs HD2XXX-HD6XXX");
+ "AMD GPUs HD2XXX-HD6XXX", "AMDGPU");
RegisterTarget<Triple::amdgcn, false> GCN(getTheGCNTarget(), "amdgcn",
- "AMD GCN GPUs");
+ "AMD GCN GPUs", "AMDGPU");
}
diff --git a/llvm/lib/Target/ARM/TargetInfo/ARMTargetInfo.cpp b/llvm/lib/Target/ARM/TargetInfo/ARMTargetInfo.cpp
index caa69f8..b0491a4 100644
--- a/llvm/lib/Target/ARM/TargetInfo/ARMTargetInfo.cpp
+++ b/llvm/lib/Target/ARM/TargetInfo/ARMTargetInfo.cpp
@@ -30,12 +30,12 @@
extern "C" void LLVMInitializeARMTargetInfo() {
RegisterTarget<Triple::arm, /*HasJIT=*/true> X(getTheARMLETarget(), "arm",
- "ARM");
+ "ARM", "ARM");
RegisterTarget<Triple::armeb, /*HasJIT=*/true> Y(getTheARMBETarget(), "armeb",
- "ARM (big endian)");
+ "ARM (big endian)", "ARM");
RegisterTarget<Triple::thumb, /*HasJIT=*/true> A(getTheThumbLETarget(),
- "thumb", "Thumb");
+ "thumb", "Thumb", "ARM");
RegisterTarget<Triple::thumbeb, /*HasJIT=*/true> B(
- getTheThumbBETarget(), "thumbeb", "Thumb (big endian)");
+ getTheThumbBETarget(), "thumbeb", "Thumb (big endian)", "ARM");
}
diff --git a/llvm/lib/Target/BPF/TargetInfo/BPFTargetInfo.cpp b/llvm/lib/Target/BPF/TargetInfo/BPFTargetInfo.cpp
index 265180b..1f7b8a0 100644
--- a/llvm/lib/Target/BPF/TargetInfo/BPFTargetInfo.cpp
+++ b/llvm/lib/Target/BPF/TargetInfo/BPFTargetInfo.cpp
@@ -28,9 +28,10 @@
extern "C" void LLVMInitializeBPFTargetInfo() {
TargetRegistry::RegisterTarget(getTheBPFTarget(), "bpf", "BPF (host endian)",
- [](Triple::ArchType) { return false; }, true);
- RegisterTarget<Triple::bpfel, /*HasJIT=*/true> X(getTheBPFleTarget(), "bpfel",
- "BPF (little endian)");
+ "BPF", [](Triple::ArchType) { return false; },
+ true);
+ RegisterTarget<Triple::bpfel, /*HasJIT=*/true> X(
+ getTheBPFleTarget(), "bpfel", "BPF (little endian)", "BPF");
RegisterTarget<Triple::bpfeb, /*HasJIT=*/true> Y(getTheBPFbeTarget(), "bpfeb",
- "BPF (big endian)");
+ "BPF (big endian)", "BPF");
}
diff --git a/llvm/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp b/llvm/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp
index 0554646..a330f27 100644
--- a/llvm/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp
+++ b/llvm/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp
@@ -18,6 +18,6 @@
}
extern "C" void LLVMInitializeHexagonTargetInfo() {
- RegisterTarget<Triple::hexagon, /*HasJIT=*/false> X(getTheHexagonTarget(),
- "hexagon", "Hexagon");
+ RegisterTarget<Triple::hexagon, /*HasJIT=*/false> X(
+ getTheHexagonTarget(), "hexagon", "Hexagon", "Hexagon");
}
diff --git a/llvm/lib/Target/Lanai/TargetInfo/LanaiTargetInfo.cpp b/llvm/lib/Target/Lanai/TargetInfo/LanaiTargetInfo.cpp
index e377db1..5eed0cb 100644
--- a/llvm/lib/Target/Lanai/TargetInfo/LanaiTargetInfo.cpp
+++ b/llvm/lib/Target/Lanai/TargetInfo/LanaiTargetInfo.cpp
@@ -21,5 +21,6 @@
} // namespace llvm
extern "C" void LLVMInitializeLanaiTargetInfo() {
- RegisterTarget<Triple::lanai> X(getTheLanaiTarget(), "lanai", "Lanai");
+ RegisterTarget<Triple::lanai> X(getTheLanaiTarget(), "lanai", "Lanai",
+ "Lanai");
}
diff --git a/llvm/lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp b/llvm/lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp
index 62f52a1..dfa21f5 100644
--- a/llvm/lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp
+++ b/llvm/lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp
@@ -19,5 +19,5 @@
extern "C" void LLVMInitializeMSP430TargetInfo() {
RegisterTarget<Triple::msp430> X(getTheMSP430Target(), "msp430",
- "MSP430 [experimental]");
+ "MSP430 [experimental]", "MSP430");
}
diff --git a/llvm/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp b/llvm/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp
index 4c1edfa..ab494d5 100644
--- a/llvm/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp
+++ b/llvm/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp
@@ -32,17 +32,17 @@
extern "C" void LLVMInitializeMipsTargetInfo() {
RegisterTarget<Triple::mips,
/*HasJIT=*/true>
- X(getTheMipsTarget(), "mips", "Mips");
+ X(getTheMipsTarget(), "mips", "Mips", "Mips");
RegisterTarget<Triple::mipsel,
/*HasJIT=*/true>
- Y(getTheMipselTarget(), "mipsel", "Mipsel");
+ Y(getTheMipselTarget(), "mipsel", "Mipsel", "Mips");
RegisterTarget<Triple::mips64,
/*HasJIT=*/true>
- A(getTheMips64Target(), "mips64", "Mips64 [experimental]");
+ A(getTheMips64Target(), "mips64", "Mips64 [experimental]", "Mips");
RegisterTarget<Triple::mips64el,
/*HasJIT=*/true>
- B(getTheMips64elTarget(), "mips64el", "Mips64el [experimental]");
+ B(getTheMips64elTarget(), "mips64el", "Mips64el [experimental]", "Mips");
}
diff --git a/llvm/lib/Target/NVPTX/TargetInfo/NVPTXTargetInfo.cpp b/llvm/lib/Target/NVPTX/TargetInfo/NVPTXTargetInfo.cpp
index d44876a..803d643 100644
--- a/llvm/lib/Target/NVPTX/TargetInfo/NVPTXTargetInfo.cpp
+++ b/llvm/lib/Target/NVPTX/TargetInfo/NVPTXTargetInfo.cpp
@@ -23,7 +23,7 @@
extern "C" void LLVMInitializeNVPTXTargetInfo() {
RegisterTarget<Triple::nvptx> X(getTheNVPTXTarget32(), "nvptx",
- "NVIDIA PTX 32-bit");
+ "NVIDIA PTX 32-bit", "NVPTX");
RegisterTarget<Triple::nvptx64> Y(getTheNVPTXTarget64(), "nvptx64",
- "NVIDIA PTX 64-bit");
+ "NVIDIA PTX 64-bit", "NVPTX");
}
diff --git a/llvm/lib/Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp b/llvm/lib/Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp
index a637dd1..9795952 100644
--- a/llvm/lib/Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp
+++ b/llvm/lib/Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp
@@ -27,11 +27,11 @@
extern "C" void LLVMInitializePowerPCTargetInfo() {
RegisterTarget<Triple::ppc, /*HasJIT=*/true> X(getThePPC32Target(), "ppc32",
- "PowerPC 32");
+ "PowerPC 32", "PPC");
RegisterTarget<Triple::ppc64, /*HasJIT=*/true> Y(getThePPC64Target(), "ppc64",
- "PowerPC 64");
+ "PowerPC 64", "PPC");
RegisterTarget<Triple::ppc64le, /*HasJIT=*/true> Z(
- getThePPC64LETarget(), "ppc64le", "PowerPC 64 LE");
+ getThePPC64LETarget(), "ppc64le", "PowerPC 64 LE", "PPC");
}
diff --git a/llvm/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp b/llvm/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp
index 66178ac..d030bd9 100644
--- a/llvm/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp
+++ b/llvm/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp
@@ -27,9 +27,9 @@
extern "C" void LLVMInitializeSparcTargetInfo() {
RegisterTarget<Triple::sparc, /*HasJIT=*/true> X(getTheSparcTarget(), "sparc",
- "Sparc");
- RegisterTarget<Triple::sparcv9, /*HasJIT=*/true> Y(getTheSparcV9Target(),
- "sparcv9", "Sparc V9");
- RegisterTarget<Triple::sparcel, /*HasJIT=*/true> Z(getTheSparcelTarget(),
- "sparcel", "Sparc LE");
+ "Sparc", "Sparc");
+ RegisterTarget<Triple::sparcv9, /*HasJIT=*/true> Y(
+ getTheSparcV9Target(), "sparcv9", "Sparc V9", "Sparc");
+ RegisterTarget<Triple::sparcel, /*HasJIT=*/true> Z(
+ getTheSparcelTarget(), "sparcel", "Sparc LE", "Sparc");
}
diff --git a/llvm/lib/Target/SystemZ/TargetInfo/SystemZTargetInfo.cpp b/llvm/lib/Target/SystemZ/TargetInfo/SystemZTargetInfo.cpp
index d3c53a4..e2b9efd 100644
--- a/llvm/lib/Target/SystemZ/TargetInfo/SystemZTargetInfo.cpp
+++ b/llvm/lib/Target/SystemZ/TargetInfo/SystemZTargetInfo.cpp
@@ -18,6 +18,6 @@
}
extern "C" void LLVMInitializeSystemZTargetInfo() {
- RegisterTarget<Triple::systemz, /*HasJIT=*/true> X(getTheSystemZTarget(),
- "systemz", "SystemZ");
+ RegisterTarget<Triple::systemz, /*HasJIT=*/true> X(
+ getTheSystemZTarget(), "systemz", "SystemZ", "SystemZ");
}
diff --git a/llvm/lib/Target/X86/TargetInfo/X86TargetInfo.cpp b/llvm/lib/Target/X86/TargetInfo/X86TargetInfo.cpp
index d2654fc..16c2b56 100644
--- a/llvm/lib/Target/X86/TargetInfo/X86TargetInfo.cpp
+++ b/llvm/lib/Target/X86/TargetInfo/X86TargetInfo.cpp
@@ -22,8 +22,8 @@
extern "C" void LLVMInitializeX86TargetInfo() {
RegisterTarget<Triple::x86, /*HasJIT=*/true> X(
- getTheX86_32Target(), "x86", "32-bit X86: Pentium-Pro and above");
+ getTheX86_32Target(), "x86", "32-bit X86: Pentium-Pro and above", "X86");
RegisterTarget<Triple::x86_64, /*HasJIT=*/true> Y(
- getTheX86_64Target(), "x86-64", "64-bit X86: EM64T and AMD64");
+ getTheX86_64Target(), "x86-64", "64-bit X86: EM64T and AMD64", "X86");
}
diff --git a/llvm/lib/Target/XCore/TargetInfo/XCoreTargetInfo.cpp b/llvm/lib/Target/XCore/TargetInfo/XCoreTargetInfo.cpp
index df5774c..41f4078 100644
--- a/llvm/lib/Target/XCore/TargetInfo/XCoreTargetInfo.cpp
+++ b/llvm/lib/Target/XCore/TargetInfo/XCoreTargetInfo.cpp
@@ -18,5 +18,6 @@
}
extern "C" void LLVMInitializeXCoreTargetInfo() {
- RegisterTarget<Triple::xcore> X(getTheXCoreTarget(), "xcore", "XCore");
+ RegisterTarget<Triple::xcore> X(getTheXCoreTarget(), "xcore", "XCore",
+ "XCore");
}