Begin to support some vector operations for AVX 256-bit intructions. The long
term goal here is to be able to match enough of vector_shuffle and build_vector
so all avx intrinsics which aren't mapped to their own built-ins but to
shufflevector calls can be codegen'd. This is the first (baby) step, support
building zeroed vectors.
llvm-svn: 110897
diff --git a/llvm/test/CodeGen/X86/avx-256.ll b/llvm/test/CodeGen/X86/avx-256.ll
new file mode 100644
index 0000000..20d31e7
--- /dev/null
+++ b/llvm/test/CodeGen/X86/avx-256.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86 -mcpu=corei7 -mattr=avx | FileCheck %s
+
+@x = common global <8 x float> zeroinitializer, align 32
+@y = common global <4 x double> zeroinitializer, align 32
+
+define void @zero() nounwind ssp {
+entry:
+ ; CHECK: vxorps
+ ; CHECK: vmovaps
+ ; CHECK: vmovaps
+ store <8 x float> zeroinitializer, <8 x float>* @x, align 32
+ store <4 x double> zeroinitializer, <4 x double>* @y, align 32
+ ret void
+}
+