commit 73156025e021f98786009a06c794f8b8f369b7a3
author Craig Topper <craig.topper@gmail.com> Sun Mar 02 09:09:27 2014 +0000
committer Craig Topper <craig.topper@gmail.com> Sun Mar 02 09:09:27 2014 +0000
tree b20fd2bf0ddc155002a79f68ef6859b54f9338b7
parent e55d9bf508471c97e7bad9e5f63e4fe103cb3042

Switch all uses of LLVM_OVERRIDE to just use 'override' directly.

llvm-svn: 202621

llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp

diff --git a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
index e78b1a2..389b123 100644
--- a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
+++ b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
@@ -162,7 +162,7 @@
   }
 
   // Token operands
-  virtual bool isToken() const LLVM_OVERRIDE {
+  virtual bool isToken() const override {
     return Kind == KindToken;
   }
   StringRef getToken() const {
@@ -171,13 +171,13 @@
   }
 
   // Register operands.
-  virtual bool isReg() const LLVM_OVERRIDE {
+  virtual bool isReg() const override {
     return Kind == KindReg;
   }
   bool isReg(RegisterKind RegKind) const {
     return Kind == KindReg && Reg.Kind == RegKind;
   }
-  virtual unsigned getReg() const LLVM_OVERRIDE {
+  virtual unsigned getReg() const override {
     assert(Kind == KindReg && "Not a register");
     return Reg.Num;
   }
@@ -189,7 +189,7 @@
   }
 
   // Immediate operands.
-  virtual bool isImm() const LLVM_OVERRIDE {
+  virtual bool isImm() const override {
     return Kind == KindImm;
   }
   bool isImm(int64_t MinValue, int64_t MaxValue) const {
@@ -201,7 +201,7 @@
   }
 
   // Memory operands.
-  virtual bool isMem() const LLVM_OVERRIDE {
+  virtual bool isMem() const override {
     return Kind == KindMem;
   }
   bool isMem(RegisterKind RegKind, MemoryKind MemKind) const {
@@ -221,9 +221,9 @@
   }
 
   // Override MCParsedAsmOperand.
-  virtual SMLoc getStartLoc() const LLVM_OVERRIDE { return StartLoc; }
-  virtual SMLoc getEndLoc() const LLVM_OVERRIDE { return EndLoc; }
-  virtual void print(raw_ostream &OS) const LLVM_OVERRIDE;
+  virtual SMLoc getStartLoc() const override { return StartLoc; }
+  virtual SMLoc getEndLoc() const override { return EndLoc; }
+  virtual void print(raw_ostream &OS) const override;
 
   // Used by the TableGen code to add particular types of operand
   // to an instruction.
@@ -340,18 +340,18 @@
   }
 
   // Override MCTargetAsmParser.
-  virtual bool ParseDirective(AsmToken DirectiveID) LLVM_OVERRIDE;
+  virtual bool ParseDirective(AsmToken DirectiveID) override;
   virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
-                             SMLoc &EndLoc) LLVM_OVERRIDE;
-  virtual bool ParseInstruction(ParseInstructionInfo &Info,
-                                StringRef Name, SMLoc NameLoc,
-                                SmallVectorImpl<MCParsedAsmOperand*> &Operands)
-    LLVM_OVERRIDE;
+                             SMLoc &EndLoc) override;
+  virtual bool
+  ParseInstruction(ParseInstructionInfo &Info,
+                   StringRef Name, SMLoc NameLoc,
+                   SmallVectorImpl<MCParsedAsmOperand*> &Operands) override;
   virtual bool
     MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                             SmallVectorImpl<MCParsedAsmOperand*> &Operands,
                             MCStreamer &Out, unsigned &ErrorInfo,
-                            bool MatchingInlineAsm) LLVM_OVERRIDE;
+                            bool MatchingInlineAsm) override;
 
   // Used by the TableGen code to parse particular operand types.
   OperandMatchResultTy