| commit | 7366fa1aa6d69a63e016abe7baec035690797f5a | [log] [tgz] |
|---|---|---|
| author | Vikram S. Adve <vadve@cs.uiuc.edu> | Tue May 27 00:05:23 2003 +0000 |
| committer | Vikram S. Adve <vadve@cs.uiuc.edu> | Tue May 27 00:05:23 2003 +0000 |
| tree | 1d91f99165555819bf5175f2b889f1285f966936 | |
| parent | 631006ba48ba5c7a4e00f3ced4a3a9d382ba1dad [diff] |
(1) Added special register class containing (for now) %fsr.
Fixed spilling of %fcc[0-3] which are part of %fsr.
(2) Moved some machine-independent reg-class code to class TargetRegInfo
from SparcReg{Class,}Info.
(3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly()
and related functions and flags. Fixed several bugs where only
"isDef" was being checked, not "isDefAndUse".
llvm-svn: 6341