misched: Added MultiIssueItineraries.
This allows a subtarget to explicitly specify the issue width and
other properties without providing pipeline stage details for every
instruction.
llvm-svn: 157979
diff --git a/llvm/lib/CodeGen/ScoreboardHazardRecognizer.cpp b/llvm/lib/CodeGen/ScoreboardHazardRecognizer.cpp
index ac62d7e..7110b75 100644
--- a/llvm/lib/CodeGen/ScoreboardHazardRecognizer.cpp
+++ b/llvm/lib/CodeGen/ScoreboardHazardRecognizer.cpp
@@ -44,8 +44,6 @@
// avoid dealing with the boundary condition.
unsigned ScoreboardDepth = 1;
if (ItinData && !ItinData->isEmpty()) {
- IssueWidth = ItinData->IssueWidth;
-
for (unsigned idx = 0; ; ++idx) {
if (ItinData->isEndMarker(idx))
break;
@@ -74,11 +72,13 @@
ReservedScoreboard.reset(ScoreboardDepth);
RequiredScoreboard.reset(ScoreboardDepth);
- if (!MaxLookAhead)
+ if (!isEnabled())
DEBUG(dbgs() << "Disabled scoreboard hazard recognizer\n");
- else
+ else {
+ IssueWidth = ItinData->Props.IssueWidth;
DEBUG(dbgs() << "Using scoreboard hazard recognizer: Depth = "
<< ScoreboardDepth << '\n');
+ }
}
void ScoreboardHazardRecognizer::Reset() {
diff --git a/llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp b/llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
index 2695163..01622cb 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
@@ -318,7 +318,7 @@
// If packet is now full, reset the state so in the next cycle
// we start fresh.
- if (Packet.size() >= InstrItins->IssueWidth) {
+ if (Packet.size() >= InstrItins->Props.IssueWidth) {
ResourcesModel->clearResources();
Packet.clear();
}
diff --git a/llvm/lib/MC/MCSubtargetInfo.cpp b/llvm/lib/MC/MCSubtargetInfo.cpp
index 86dc108..cb56a54 100644
--- a/llvm/lib/MC/MCSubtargetInfo.cpp
+++ b/llvm/lib/MC/MCSubtargetInfo.cpp
@@ -91,6 +91,8 @@
return InstrItineraryData();
}
- return InstrItineraryData(Stages, OperandCycles, ForwardingPathes,
- (InstrItinerary *)Found->Value);
+ InstrItinerarySubtargetValue *V =
+ (InstrItinerarySubtargetValue *)Found->Value;
+ return InstrItineraryData(V->Props, Stages, OperandCycles, ForwardingPathes,
+ V->Itineraries);
}
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp
index ac568b1..0bea9e4b 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -200,13 +200,14 @@
const InstrStage *IS = InstrItins.Stages + itin->FirstStage;
allStage1Units |= IS->getUnits();
}
- InstrItins.IssueWidth = 0;
+ InstrItins.Props.IssueWidth = 0;
while (allStage1Units) {
- ++InstrItins.IssueWidth;
+ ++InstrItins.Props.IssueWidth;
// clear the lowest bit
allStage1Units ^= allStage1Units & ~(allStage1Units - 1);
}
- assert(InstrItins.IssueWidth <= 2 && "itinerary bug, too many stage 1 units");
+ assert(InstrItins.Props.IssueWidth <= 2 &&
+ "itinerary bug, too many stage 1 units");
}
bool ARMSubtarget::enablePostRAScheduler(
diff --git a/llvm/lib/Target/Hexagon/HexagonSchedule.td b/llvm/lib/Target/Hexagon/HexagonSchedule.td
index c488796..b4df678 100644
--- a/llvm/lib/Target/Hexagon/HexagonSchedule.td
+++ b/llvm/lib/Target/Hexagon/HexagonSchedule.td
@@ -41,7 +41,10 @@
InstrItinData<SYS , [InstrStage<1, [LSUNIT]>]>,
InstrItinData<MARKER , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>,
InstrItinData<PSEUDO , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>
- ]>;
+ ]> {
+ // Max issue per cycle == bundle width.
+ let IssueWidth = 4;
+}
//===----------------------------------------------------------------------===//
// V4 Machine Info +
diff --git a/llvm/lib/Target/Hexagon/HexagonScheduleV4.td b/llvm/lib/Target/Hexagon/HexagonScheduleV4.td
index 1d82dbb..8d6f7b2 100644
--- a/llvm/lib/Target/Hexagon/HexagonScheduleV4.td
+++ b/llvm/lib/Target/Hexagon/HexagonScheduleV4.td
@@ -52,7 +52,11 @@
InstrItinData<MARKER , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
InstrItinData<PREFIX , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>
- ]>;
+ ]> {
+ // Max issue per cycle == bundle width.
+ let IssueWidth = 4;
+}
+
//===----------------------------------------------------------------------===//
// Hexagon V4 Resource Definitions -
diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
index 8744b7b..ce81a78 100644
--- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
@@ -61,9 +61,6 @@
// Initialize scheduling itinerary for the specified CPU.
InstrItins = getInstrItineraryForCPU(CPUString);
- // Max issue per cycle == bundle width.
- InstrItins.IssueWidth = 4;
-
if (EnableMemOps)
UseMemOps = true;
else
diff --git a/llvm/lib/Target/MBlaze/MBlazeSubtarget.cpp b/llvm/lib/Target/MBlaze/MBlazeSubtarget.cpp
index d12d142..dc2ad29 100644
--- a/llvm/lib/Target/MBlaze/MBlazeSubtarget.cpp
+++ b/llvm/lib/Target/MBlaze/MBlazeSubtarget.cpp
@@ -43,13 +43,6 @@
// Initialize scheduling itinerary for the specified CPU.
InstrItins = getInstrItineraryForCPU(CPUName);
-
- // Compute the issue width of the MBlaze itineraries
- computeIssueWidth();
-}
-
-void MBlazeSubtarget::computeIssueWidth() {
- InstrItins.IssueWidth = 1;
}
bool MBlazeSubtarget::