[X86][Disassembler] Clamp index to 4-bits when decoding GPR registers.
A 5-bit value can occur when EVEX.X is 0 due to it being used to extend modrm.rm to encode XMM16-31. But if modrm.rm instead encodes a GPR, the Intel documentation says EVEX.X should be ignored so just mask it to 4 bits once we know its a GPR.
llvm-svn: 333725
diff --git a/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp b/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
index 191310a..5be43fa 100644
--- a/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
+++ b/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
@@ -1459,6 +1459,7 @@
case TYPE_Rv: \
return base + index; \
case TYPE_R8: \
+ index &= 0xf; \
if (insn->rexPrefix && \
index >= 4 && index <= 7) { \
return prefix##_SPL + (index - 4); \
@@ -1466,11 +1467,11 @@
return prefix##_AL + index; \
} \
case TYPE_R16: \
- return prefix##_AX + index; \
+ return prefix##_AX + (index & 0xf); \
case TYPE_R32: \
- return prefix##_EAX + index; \
+ return prefix##_EAX + (index & 0xf); \
case TYPE_R64: \
- return prefix##_RAX + index; \
+ return prefix##_RAX + (index & 0xf); \
case TYPE_ZMM: \
return prefix##_ZMM0 + index; \
case TYPE_YMM: \