[NFC][X86][AArch64] A few more patterns for [lack of] signed truncation check pattern.[NFC][X86][AArch64] A few more patterns for [lack of] signed truncation check pattern.
llvm-svn: 341188
diff --git a/llvm/test/CodeGen/X86/signed-truncation-check.ll b/llvm/test/CodeGen/X86/signed-truncation-check.ll
index c41b4e6..4684770 100644
--- a/llvm/test/CodeGen/X86/signed-truncation-check.ll
+++ b/llvm/test/CodeGen/X86/signed-truncation-check.ll
@@ -11,7 +11,7 @@
; This can be expressed in a several ways in IR:
; trunc + sext + icmp eq <- not canonical
; shl + ashr + icmp eq
-; add + icmp uge
+; add + icmp uge/ugt
; add + icmp ult/ule
; However only the simplest form (with two shifts) gets lowered best.
@@ -292,6 +292,29 @@
ret i1 %tmp1
}
+; Slightly more canonical variant
+define i1 @add_ugtcmp_i16_i8(i16 %x) nounwind {
+; X86-LABEL: add_ugtcmp_i16_i8:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: addl $-128, %eax
+; X86-NEXT: movzwl %ax, %eax
+; X86-NEXT: cmpl $65279, %eax # imm = 0xFEFF
+; X86-NEXT: seta %al
+; X86-NEXT: retl
+;
+; X64-LABEL: add_ugtcmp_i16_i8:
+; X64: # %bb.0:
+; X64-NEXT: addl $-128, %edi
+; X64-NEXT: movzwl %di, %eax
+; X64-NEXT: cmpl $65279, %eax # imm = 0xFEFF
+; X64-NEXT: seta %al
+; X64-NEXT: retq
+ %tmp0 = add i16 %x, -128 ; ~0U << (8-1)
+ %tmp1 = icmp ugt i16 %tmp0, -257 ; ~0U << 8 - 1
+ ret i1 %tmp1
+}
+
; ---------------------------------------------------------------------------- ;
; add + icmp ult
; ---------------------------------------------------------------------------- ;