[ARM]Decoding MSR with unpredictable destination register causes an assert
This patch handling:
Enable parsing of raw encodings of system registers .
Allows UNPREDICTABLE sysregs to be decoded to a raw number in the same way that disasslib does, rather than llvm crashing.
Disassemble msr/mrs with unpredictable sysregs as SoftFail.
Fix regression due to SoftFailing some encodings.
Patch by Chris Ryder
Differential revision:https://reviews.llvm.org/D43374
llvm-svn: 326803
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index f9a0a74..3ffa702 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -4149,7 +4149,6 @@
case 0x8a: // msplim_ns
case 0x8b: // psplim_ns
case 0x91: // basepri_ns
- case 0x92: // basepri_max_ns
case 0x93: // faultmask_ns
if (!(FeatureBits[ARM::HasV8MMainlineOps]))
return MCDisassembler::Fail;
@@ -4165,7 +4164,9 @@
return MCDisassembler::Fail;
break;
default:
- return MCDisassembler::Fail;
+ // Architecturally defined as unpredictable
+ S = MCDisassembler::SoftFail;
+ break;
}
if (Inst.getOpcode() == ARM::t2MSR_M) {