diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index f15ce57..1e5499a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -216,7 +216,7 @@
     }
     return false;
   case ISD::ADD:
-    // (add X, Y) & C == 0 iff (X&C)&(Y&C) == 0 and all bits are low bits.
+    // (add X, Y) & C == 0 iff (X&C)|(Y&C) == 0 and all bits are low bits.
     if ((Mask&(Mask+1)) == 0) {  // All low bits
       if (MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
           MaskedValueIsZero(Op.getOperand(1), Mask, TLI))