Use std::bitset for SubtargetFeatures
Previously, subtarget features were a bitfield with the underlying type being uint64_t.
Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset.
No functional change.
The first time this was committed (r229831), it caused several buildbot failures.
At least some of the ARM ones were due to gcc/binutils issues, and should now be fixed.
Differential Revision: http://reviews.llvm.org/D8542
llvm-svn: 233055
diff --git a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
index bc6c7a9..d127773 100644
--- a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
+++ b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
@@ -14,6 +14,7 @@
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringExtras.h"
+#include "llvm/MC/SubtargetFeature.h"
#include "llvm/Support/Regex.h"
using namespace llvm;
@@ -245,7 +246,7 @@
{"ich_elsr_el2", ICH_ELSR_EL2}
};
-AArch64SysReg::MRSMapper::MRSMapper(uint64_t FeatureBits)
+AArch64SysReg::MRSMapper::MRSMapper(const FeatureBitset &FeatureBits)
: SysRegMapper(FeatureBits) {
InstPairs = &MRSPairs[0];
NumInstPairs = llvm::array_lengthof(MRSPairs);
@@ -269,7 +270,7 @@
{"icc_sgi0r_el1", ICC_SGI0R_EL1}
};
-AArch64SysReg::MSRMapper::MSRMapper(uint64_t FeatureBits)
+AArch64SysReg::MSRMapper::MSRMapper(const FeatureBitset &FeatureBits)
: SysRegMapper(FeatureBits) {
InstPairs = &MSRPairs[0];
NumInstPairs = llvm::array_lengthof(MSRPairs);
@@ -773,7 +774,7 @@
}
// Next search for target specific registers
- if (FeatureBits & AArch64::ProcCyclone) {
+ if (FeatureBits[AArch64::ProcCyclone]) {
for (unsigned i = 0; i < array_lengthof(CycloneSysRegPairs); ++i) {
if (CycloneSysRegPairs[i].Name == NameLower) {
Valid = true;
@@ -823,7 +824,7 @@
}
// Next search for target specific registers
- if (FeatureBits & AArch64::ProcCyclone) {
+ if (FeatureBits[AArch64::ProcCyclone]) {
for (unsigned i = 0; i < array_lengthof(CycloneSysRegPairs); ++i) {
if (CycloneSysRegPairs[i].Value == Bits) {
return CycloneSysRegPairs[i].Name;
diff --git a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
index 6d0337c..4e80a79 100644
--- a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+++ b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
@@ -26,6 +26,8 @@
namespace llvm {
+class FeatureBitset;
+
inline static unsigned getWRegFromXReg(unsigned Reg) {
switch (Reg) {
case AArch64::X0: return AArch64::W0;
@@ -1139,21 +1141,21 @@
const AArch64NamedImmMapper::Mapping *InstPairs;
size_t NumInstPairs;
- uint64_t FeatureBits;
+ const FeatureBitset &FeatureBits;
- SysRegMapper(uint64_t FeatureBits) : FeatureBits(FeatureBits) { }
+ SysRegMapper(const FeatureBitset &FeatureBits) : FeatureBits(FeatureBits) { }
uint32_t fromString(StringRef Name, bool &Valid) const;
std::string toString(uint32_t Bits) const;
};
struct MSRMapper : SysRegMapper {
static const AArch64NamedImmMapper::Mapping MSRPairs[];
- MSRMapper(uint64_t FeatureBits);
+ MSRMapper(const FeatureBitset &FeatureBits);
};
struct MRSMapper : SysRegMapper {
static const AArch64NamedImmMapper::Mapping MRSPairs[];
- MRSMapper(uint64_t FeatureBits);
+ MRSMapper(const FeatureBitset &FeatureBits);
};
uint32_t ParseGenericRegister(StringRef Name, bool &Valid);
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
index 971e10d..e21135c 100644
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -420,7 +420,7 @@
}
static bool isThumb(const MCSubtargetInfo& STI) {
- return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
+ return STI.getFeatureBits()[ARM::ModeThumb];
}
void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 7ee3cb0..1dfc619 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -4513,7 +4513,7 @@
}
bool ARMBaseInstrInfo::hasNOP() const {
- return (Subtarget.getFeatureBits() & ARM::HasV6KOps) != 0;
+ return Subtarget.getFeatureBits()[ARM::HasV6KOps];
}
bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp
index 3b0d787..a994869 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -263,8 +263,8 @@
}
// NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
- uint64_t Bits = getFeatureBits();
- if ((Bits & ARM::ProcA5 || Bits & ARM::ProcA8) && // Where this matters
+ const FeatureBitset &Bits = getFeatureBits();
+ if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
(Options.UnsafeFPMath || isTargetDarwin()))
UseNEONForSinglePrecisionFP = true;
}
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index f7d397b..61dde57 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -244,37 +244,37 @@
bool isThumb() const {
// FIXME: Can tablegen auto-generate this?
- return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
+ return STI.getFeatureBits()[ARM::ModeThumb];
}
bool isThumbOne() const {
- return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
+ return isThumb() && !STI.getFeatureBits()[ARM::FeatureThumb2];
}
bool isThumbTwo() const {
- return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
+ return isThumb() && STI.getFeatureBits()[ARM::FeatureThumb2];
}
bool hasThumb() const {
- return STI.getFeatureBits() & ARM::HasV4TOps;
+ return STI.getFeatureBits()[ARM::HasV4TOps];
}
bool hasV6Ops() const {
- return STI.getFeatureBits() & ARM::HasV6Ops;
+ return STI.getFeatureBits()[ARM::HasV6Ops];
}
bool hasV6MOps() const {
- return STI.getFeatureBits() & ARM::HasV6MOps;
+ return STI.getFeatureBits()[ARM::HasV6MOps];
}
bool hasV7Ops() const {
- return STI.getFeatureBits() & ARM::HasV7Ops;
+ return STI.getFeatureBits()[ARM::HasV7Ops];
}
bool hasV8Ops() const {
- return STI.getFeatureBits() & ARM::HasV8Ops;
+ return STI.getFeatureBits()[ARM::HasV8Ops];
}
bool hasARM() const {
- return !(STI.getFeatureBits() & ARM::FeatureNoARM);
+ return !STI.getFeatureBits()[ARM::FeatureNoARM];
}
bool hasThumb2DSP() const {
- return STI.getFeatureBits() & ARM::FeatureDSPThumb2;
+ return STI.getFeatureBits()[ARM::FeatureDSPThumb2];
}
bool hasD16() const {
- return STI.getFeatureBits() & ARM::FeatureD16;
+ return STI.getFeatureBits()[ARM::FeatureD16];
}
void SwitchMode() {
@@ -282,7 +282,7 @@
setAvailableFeatures(FB);
}
bool isMClass() const {
- return STI.getFeatureBits() & ARM::FeatureMClass;
+ return STI.getFeatureBits()[ARM::FeatureMClass];
}
/// @name Auto-generated Match Functions
@@ -9186,52 +9186,53 @@
// tools/clang/lib/Driver/Tools.cpp
static const struct {
const unsigned ID;
- const uint64_t Enabled;
- const uint64_t Disabled;
+ const FeatureBitset Enabled;
+ const FeatureBitset Disabled;
} FPUs[] = {
- {/* ID */ ARM::VFP,
- /* Enabled */ ARM::FeatureVFP2,
- /* Disabled */ ARM::FeatureNEON},
- {/* ID */ ARM::VFPV2,
- /* Enabled */ ARM::FeatureVFP2,
- /* Disabled */ ARM::FeatureNEON},
- {/* ID */ ARM::VFPV3,
- /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3,
- /* Disabled */ ARM::FeatureNEON | ARM::FeatureD16},
- {/* ID */ ARM::VFPV3_D16,
- /* Enable */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureD16,
- /* Disabled */ ARM::FeatureNEON},
- {/* ID */ ARM::VFPV4,
- /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4,
- /* Disabled */ ARM::FeatureNEON | ARM::FeatureD16},
- {/* ID */ ARM::VFPV4_D16,
- /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
- ARM::FeatureD16,
- /* Disabled */ ARM::FeatureNEON},
- {/* ID */ ARM::FPV5_D16,
- /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
- ARM::FeatureFPARMv8 | ARM::FeatureD16,
- /* Disabled */ ARM::FeatureNEON | ARM::FeatureCrypto},
- {/* ID */ ARM::FP_ARMV8,
- /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
- ARM::FeatureFPARMv8,
- /* Disabled */ ARM::FeatureNEON | ARM::FeatureCrypto | ARM::FeatureD16},
- {/* ID */ ARM::NEON,
- /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureNEON,
- /* Disabled */ ARM::FeatureD16},
- {/* ID */ ARM::NEON_VFPV4,
- /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
- ARM::FeatureNEON,
- /* Disabled */ ARM::FeatureD16},
- {/* ID */ ARM::NEON_FP_ARMV8,
- /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
- ARM::FeatureFPARMv8 | ARM::FeatureNEON,
- /* Disabled */ ARM::FeatureCrypto | ARM::FeatureD16},
- {/* ID */ ARM::CRYPTO_NEON_FP_ARMV8,
- /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
- ARM::FeatureFPARMv8 | ARM::FeatureNEON | ARM::FeatureCrypto,
- /* Disabled */ ARM::FeatureD16},
- {ARM::SOFTVFP, 0, 0},
+ {/* ID */ ARM::VFP,
+ /* Enabled */ {ARM::FeatureVFP2},
+ /* Disabled */ {ARM::FeatureNEON}},
+ {/* ID */ ARM::VFPV2,
+ /* Enabled */ {ARM::FeatureVFP2},
+ /* Disabled */ {ARM::FeatureNEON}},
+ {/* ID */ ARM::VFPV3,
+ /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3},
+ /* Disabled */ {ARM::FeatureNEON, ARM::FeatureD16}},
+ {/* ID */ ARM::VFPV3_D16,
+ /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureD16},
+ /* Disabled */ {ARM::FeatureNEON}},
+ {/* ID */ ARM::VFPV4,
+ /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4},
+ /* Disabled */ {ARM::FeatureNEON, ARM::FeatureD16}},
+ {/* ID */ ARM::VFPV4_D16,
+ /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4,
+ ARM::FeatureD16},
+ /* Disabled */ {ARM::FeatureNEON}},
+ {/* ID */ ARM::FPV5_D16,
+ /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4,
+ ARM::FeatureFPARMv8, ARM::FeatureD16},
+ /* Disabled */ {ARM::FeatureNEON, ARM::FeatureCrypto}},
+ {/* ID */ ARM::FP_ARMV8,
+ /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4,
+ ARM::FeatureFPARMv8},
+ /* Disabled */ {ARM::FeatureNEON, ARM::FeatureCrypto, ARM::FeatureD16}},
+ {/* ID */ ARM::NEON,
+ /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureNEON},
+ /* Disabled */ {ARM::FeatureD16}},
+ {/* ID */ ARM::NEON_VFPV4,
+ /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4,
+ ARM::FeatureNEON},
+ /* Disabled */ {ARM::FeatureD16}},
+ {/* ID */ ARM::NEON_FP_ARMV8,
+ /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4,
+ ARM::FeatureFPARMv8, ARM::FeatureNEON},
+ /* Disabled */ {ARM::FeatureCrypto, ARM::FeatureD16}},
+ {/* ID */ ARM::CRYPTO_NEON_FP_ARMV8,
+ /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4,
+ ARM::FeatureFPARMv8, ARM::FeatureNEON,
+ ARM::FeatureCrypto},
+ /* Disabled */ {ARM::FeatureD16}},
+ {ARM::SOFTVFP, {}, {}},
};
/// parseDirectiveFPU
@@ -9256,8 +9257,8 @@
// Need to toggle features that should be on but are off and that
// should off but are on.
- uint64_t Toggle = (Entry.Enabled & ~STI.getFeatureBits()) |
- (Entry.Disabled & STI.getFeatureBits());
+ FeatureBitset Toggle = (Entry.Enabled & ~STI.getFeatureBits()) |
+ (Entry.Disabled & STI.getFeatureBits());
setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature(Toggle)));
break;
}
@@ -9994,30 +9995,30 @@
static const struct {
const char *Name;
const unsigned ArchCheck;
- const uint64_t Features;
+ const FeatureBitset Features;
} Extensions[] = {
- { "crc", Feature_HasV8, ARM::FeatureCRC },
+ { "crc", Feature_HasV8, {ARM::FeatureCRC} },
{ "crypto", Feature_HasV8,
- ARM::FeatureCrypto | ARM::FeatureNEON | ARM::FeatureFPARMv8 },
- { "fp", Feature_HasV8, ARM::FeatureFPARMv8 },
+ {ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8} },
+ { "fp", Feature_HasV8, {ARM::FeatureFPARMv8} },
{ "idiv", Feature_HasV7 | Feature_IsNotMClass,
- ARM::FeatureHWDiv | ARM::FeatureHWDivARM },
+ {ARM::FeatureHWDiv, ARM::FeatureHWDivARM} },
// FIXME: iWMMXT not supported
- { "iwmmxt", Feature_None, 0 },
+ { "iwmmxt", Feature_None, {} },
// FIXME: iWMMXT2 not supported
- { "iwmmxt2", Feature_None, 0 },
+ { "iwmmxt2", Feature_None, {} },
// FIXME: Maverick not supported
- { "maverick", Feature_None, 0 },
- { "mp", Feature_HasV7 | Feature_IsNotMClass, ARM::FeatureMP },
+ { "maverick", Feature_None, {} },
+ { "mp", Feature_HasV7 | Feature_IsNotMClass, {ARM::FeatureMP} },
// FIXME: ARMv6-m OS Extensions feature not checked
- { "os", Feature_None, 0 },
+ { "os", Feature_None, {} },
// FIXME: Also available in ARMv6-K
- { "sec", Feature_HasV7, ARM::FeatureTrustZone },
- { "simd", Feature_HasV8, ARM::FeatureNEON | ARM::FeatureFPARMv8 },
+ { "sec", Feature_HasV7, {ARM::FeatureTrustZone} },
+ { "simd", Feature_HasV8, {ARM::FeatureNEON, ARM::FeatureFPARMv8} },
// FIXME: Only available in A-class, isel not predicated
- { "virt", Feature_HasV7, ARM::FeatureVirtualization },
+ { "virt", Feature_HasV7, {ARM::FeatureVirtualization} },
// FIXME: xscale not supported
- { "xscale", Feature_None, 0 },
+ { "xscale", Feature_None, {} },
};
/// parseDirectiveArchExtension
@@ -10045,7 +10046,7 @@
if (Extension.Name != Name)
continue;
- if (!Extension.Features)
+ if (Extension.Features.none())
report_fatal_error("unsupported architectural extension: " + Name);
if ((getAvailableFeatures() & Extension.ArchCheck) != Extension.ArchCheck) {
@@ -10054,9 +10055,10 @@
return false;
}
- uint64_t ToggleFeatures = EnableFeature
- ? (~STI.getFeatureBits() & Extension.Features)
- : ( STI.getFeatureBits() & Extension.Features);
+ FeatureBitset ToggleFeatures = EnableFeature
+ ? (~STI.getFeatureBits() & Extension.Features)
+ : ( STI.getFeatureBits() & Extension.Features);
+
uint64_t Features =
ComputeAvailableFeatures(STI.ToggleFeature(ToggleFeatures));
setAvailableFeatures(Features);
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 4d5122a..bd04422 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -431,7 +431,7 @@
raw_ostream &CS) const {
CommentStream = &CS;
- assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
+ assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
"Asked to disassemble an ARM instruction but Subtarget is in Thumb "
"mode!");
@@ -696,7 +696,7 @@
raw_ostream &CS) const {
CommentStream = &CS;
- assert((STI.getFeatureBits() & ARM::ModeThumb) &&
+ assert(STI.getFeatureBits()[ARM::ModeThumb] &&
"Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
// We want to read exactly 2 bytes of data.
@@ -1022,9 +1022,10 @@
static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) {
- uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
- .getFeatureBits();
- bool hasD16 = featureBits & ARM::FeatureD16;
+ const FeatureBitset &featureBits =
+ ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
+
+ bool hasD16 = featureBits[ARM::FeatureD16];
if (RegNo > 31 || (hasD16 && RegNo > 15))
return MCDisassembler::Fail;
@@ -1369,9 +1370,9 @@
break;
}
- uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
- .getFeatureBits();
- if ((featureBits & ARM::HasV8Ops) && (coproc != 14))
+ const FeatureBitset &featureBits =
+ ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
+ if (featureBits[ARM::HasV8Ops] && (coproc != 14))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(coproc));
@@ -3267,10 +3268,11 @@
unsigned Rt = fieldFromInstruction(Insn, 12, 4);
unsigned Rn = fieldFromInstruction(Insn, 16, 4);
- uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
- .getFeatureBits();
- bool hasMP = featureBits & ARM::FeatureMP;
- bool hasV7Ops = featureBits & ARM::HasV7Ops;
+ const FeatureBitset &featureBits =
+ ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
+
+ bool hasMP = featureBits[ARM::FeatureMP];
+ bool hasV7Ops = featureBits[ARM::HasV7Ops];
if (Rn == 15) {
switch (Inst.getOpcode()) {
@@ -3353,10 +3355,11 @@
imm |= (Rn << 9);
unsigned add = fieldFromInstruction(Insn, 9, 1);
- uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
- .getFeatureBits();
- bool hasMP = featureBits & ARM::FeatureMP;
- bool hasV7Ops = featureBits & ARM::HasV7Ops;
+ const FeatureBitset &featureBits =
+ ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
+
+ bool hasMP = featureBits[ARM::FeatureMP];
+ bool hasV7Ops = featureBits[ARM::HasV7Ops];
if (Rn == 15) {
switch (Inst.getOpcode()) {
@@ -3433,10 +3436,11 @@
unsigned imm = fieldFromInstruction(Insn, 0, 12);
imm |= (Rn << 13);
- uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
- .getFeatureBits();
- bool hasMP = (featureBits & ARM::FeatureMP);
- bool hasV7Ops = (featureBits & ARM::HasV7Ops);
+ const FeatureBitset &featureBits =
+ ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
+
+ bool hasMP = featureBits[ARM::FeatureMP];
+ bool hasV7Ops = featureBits[ARM::HasV7Ops];
if (Rn == 15) {
switch (Inst.getOpcode()) {
@@ -3550,9 +3554,10 @@
unsigned U = fieldFromInstruction(Insn, 23, 1);
int imm = fieldFromInstruction(Insn, 0, 12);
- uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
- .getFeatureBits();
- bool hasV7Ops = (featureBits & ARM::HasV7Ops);
+ const FeatureBitset &featureBits =
+ ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
+
+ bool hasV7Ops = featureBits[ARM::HasV7Ops];
if (Rt == 15) {
switch (Inst.getOpcode()) {
@@ -3873,9 +3878,10 @@
if (Val == 0xA || Val == 0xB)
return MCDisassembler::Fail;
- uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
- .getFeatureBits();
- if ((featureBits & ARM::HasV8Ops) && !(Val == 14 || Val == 15))
+ const FeatureBitset &featureBits =
+ ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
+
+ if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(Val));
@@ -4025,9 +4031,10 @@
static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success;
- uint64_t FeatureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
- .getFeatureBits();
- if (FeatureBits & ARM::FeatureMClass) {
+ const FeatureBitset &FeatureBits =
+ ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
+
+ if (FeatureBits[ARM::FeatureMClass]) {
unsigned ValLow = Val & 0xff;
// Validate the SYSm value first.
@@ -4047,7 +4054,7 @@
case 17: // basepri
case 18: // basepri_max
case 19: // faultmask
- if (!(FeatureBits & ARM::HasV7Ops))
+ if (!(FeatureBits[ARM::HasV7Ops]))
// Values basepri, basepri_max and faultmask are only valid for v7m.
return MCDisassembler::Fail;
break;
@@ -4057,7 +4064,7 @@
if (Inst.getOpcode() == ARM::t2MSR_M) {
unsigned Mask = fieldFromInstruction(Val, 10, 2);
- if (!(FeatureBits & ARM::HasV7Ops)) {
+ if (!(FeatureBits[ARM::HasV7Ops])) {
// The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
// unpredictable.
if (Mask != 2)
@@ -4071,7 +4078,7 @@
// indicates the move for the GE{3:0} bits, the mask{0} bit can be set
// only if the processor includes the DSP extension.
if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
- (!(FeatureBits & ARM::FeatureDSPThumb2) && (Mask & 1)))
+ (!(FeatureBits[ARM::FeatureDSPThumb2]) && (Mask & 1)))
S = MCDisassembler::SoftFail;
}
}
diff --git a/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
index 16eea33..41287df 100644
--- a/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
+++ b/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
@@ -90,7 +90,7 @@
case 3: O << "\twfi"; break;
case 4: O << "\tsev"; break;
case 5:
- if ((getAvailableFeatures() & ARM::HasV8Ops)) {
+ if (getAvailableFeatures()[ARM::HasV8Ops]) {
O << "\tsevl";
break;
} // Fallthrough for non-v8
@@ -299,7 +299,7 @@
if (MI->getNumOperands() == 3 &&
MI->getOperand(0).isImm() &&
MI->getOperand(0).getImm() == 0 &&
- (getAvailableFeatures() & ARM::FeatureVirtualization)) {
+ getAvailableFeatures()[ARM::FeatureVirtualization]) {
O << "\teret";
printPredicateOperand(MI, 1, O);
printAnnotation(O, Annot);
@@ -698,7 +698,7 @@
void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
unsigned val = MI->getOperand(OpNum).getImm();
- O << ARM_MB::MemBOptToString(val, (getAvailableFeatures() & ARM::HasV8Ops));
+ O << ARM_MB::MemBOptToString(val, getAvailableFeatures()[ARM::HasV8Ops]);
}
void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned OpNum,
@@ -796,14 +796,14 @@
const MCOperand &Op = MI->getOperand(OpNum);
unsigned SpecRegRBit = Op.getImm() >> 4;
unsigned Mask = Op.getImm() & 0xf;
- uint64_t FeatureBits = getAvailableFeatures();
+ const FeatureBitset &FeatureBits = getAvailableFeatures();
- if (FeatureBits & ARM::FeatureMClass) {
+ if (FeatureBits[ARM::FeatureMClass]) {
unsigned SYSm = Op.getImm();
unsigned Opcode = MI->getOpcode();
// For writes, handle extended mask bits if the DSP extension is present.
- if (Opcode == ARM::t2MSR_M && (FeatureBits & ARM::FeatureDSPThumb2)) {
+ if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSPThumb2]) {
switch (SYSm) {
case 0x400: O << "apsr_g"; return;
case 0xc00: O << "apsr_nzcvqg"; return;
@@ -819,7 +819,7 @@
// Handle the basic 8-bit mask.
SYSm &= 0xff;
- if (Opcode == ARM::t2MSR_M && (FeatureBits & ARM::HasV7Ops)) {
+ if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) {
// ARMv7-M deprecates using MSR APSR without a _<bits> qualifier as an
// alias for MSR APSR_nzcvq.
switch (SYSm) {
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
index f4f1082..1246cc4 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
@@ -33,7 +33,7 @@
return ARM::NumTargetFixupKinds;
}
- bool hasNOP() const { return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0; }
+ bool hasNOP() const { return STI->getFeatureBits()[ARM::HasV6T2Ops]; }
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
index e48cabbf..4d1bec3 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
@@ -51,10 +51,10 @@
~ARMMCCodeEmitter() {}
bool isThumb(const MCSubtargetInfo &STI) const {
- return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
+ return STI.getFeatureBits()[ARM::ModeThumb];
}
bool isThumb2(const MCSubtargetInfo &STI) const {
- return isThumb(STI) && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
+ return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2];
}
bool isTargetMachO(const MCSubtargetInfo &STI) const {
Triple TT(STI.getTargetTriple());
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
index 82dac5c..3ecd559 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
@@ -33,7 +33,7 @@
static bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
std::string &Info) {
- if (STI.getFeatureBits() & llvm::ARM::HasV7Ops &&
+ if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
(MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
(MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
// Checks for the deprecated CP15ISB encoding:
@@ -65,7 +65,7 @@
static bool getITDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
std::string &Info) {
- if (STI.getFeatureBits() & llvm::ARM::HasV8Ops && MI.getOperand(1).isImm() &&
+ if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() &&
MI.getOperand(1).getImm() != 8) {
Info = "applying IT instruction to more than one subsequent instruction is "
"deprecated";
@@ -77,7 +77,7 @@
static bool getARMStoreDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
std::string &Info) {
- assert((~STI.getFeatureBits() & llvm::ARM::ModeThumb) &&
+ assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
"cannot predicate thumb instructions");
assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
@@ -94,7 +94,7 @@
static bool getARMLoadDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
std::string &Info) {
- assert((~STI.getFeatureBits() & llvm::ARM::ModeThumb) &&
+ assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
"cannot predicate thumb instructions");
assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index a502466..7f3858a 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -72,15 +72,7 @@
// The full table can be found in MipsGenSubtargetInfo.inc (MipsFeatureKV[]).
// The reason we need this mask is explained in the selectArch function.
// FIXME: Ideally we would like TableGen to generate this information.
- static const uint64_t AllArchRelatedMask =
- Mips::FeatureMips1 | Mips::FeatureMips2 | Mips::FeatureMips3 |
- Mips::FeatureMips3_32 | Mips::FeatureMips3_32r2 | Mips::FeatureMips4 |
- Mips::FeatureMips4_32 | Mips::FeatureMips4_32r2 | Mips::FeatureMips5 |
- Mips::FeatureMips5_32r2 | Mips::FeatureMips32 | Mips::FeatureMips32r2 |
- Mips::FeatureMips32r3 | Mips::FeatureMips32r5 | Mips::FeatureMips32r6 |
- Mips::FeatureMips64 | Mips::FeatureMips64r2 | Mips::FeatureMips64r3 |
- Mips::FeatureMips64r5 | Mips::FeatureMips64r6 | Mips::FeatureCnMips |
- Mips::FeatureFP64Bit | Mips::FeatureGP64Bit | Mips::FeatureNaN2008;
+ static const FeatureBitset AllArchRelatedMask;
private:
unsigned ATReg;
@@ -90,6 +82,17 @@
};
}
+const FeatureBitset MipsAssemblerOptions::AllArchRelatedMask = {
+ Mips::FeatureMips1, Mips::FeatureMips2, Mips::FeatureMips3,
+ Mips::FeatureMips3_32, Mips::FeatureMips3_32r2, Mips::FeatureMips4,
+ Mips::FeatureMips4_32, Mips::FeatureMips4_32r2, Mips::FeatureMips5,
+ Mips::FeatureMips5_32r2, Mips::FeatureMips32, Mips::FeatureMips32r2,
+ Mips::FeatureMips32r3, Mips::FeatureMips32r5, Mips::FeatureMips32r6,
+ Mips::FeatureMips64, Mips::FeatureMips64r2, Mips::FeatureMips64r3,
+ Mips::FeatureMips64r5, Mips::FeatureMips64r6, Mips::FeatureCnMips,
+ Mips::FeatureFP64Bit, Mips::FeatureGP64Bit, Mips::FeatureNaN2008
+};
+
namespace {
class MipsAsmParser : public MCTargetAsmParser {
MipsTargetStreamer &getTargetStreamer() {
@@ -299,7 +302,7 @@
// FeatureMipsGP64 | FeatureMips1)
// Clearing Mips3 is equivalent to clear (FeatureMips3 | FeatureMips4).
void selectArch(StringRef ArchFeature) {
- uint64_t FeatureBits = STI.getFeatureBits();
+ FeatureBitset FeatureBits = STI.getFeatureBits();
FeatureBits &= ~MipsAssemblerOptions::AllArchRelatedMask;
STI.setFeatureBits(FeatureBits);
setAvailableFeatures(
@@ -308,7 +311,7 @@
}
void setFeatureBits(uint64_t Feature, StringRef FeatureString) {
- if (!(STI.getFeatureBits() & Feature)) {
+ if (!(STI.getFeatureBits()[Feature])) {
setAvailableFeatures(
ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
}
@@ -316,7 +319,7 @@
}
void clearFeatureBits(uint64_t Feature, StringRef FeatureString) {
- if (STI.getFeatureBits() & Feature) {
+ if (STI.getFeatureBits()[Feature]) {
setAvailableFeatures(
ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
}
@@ -361,65 +364,66 @@
/// True if all of $fcc0 - $fcc7 exist for the current ISA.
bool hasEightFccRegisters() const { return hasMips4() || hasMips32(); }
- bool isGP64bit() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
- bool isFP64bit() const { return STI.getFeatureBits() & Mips::FeatureFP64Bit; }
+ bool isGP64bit() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
+ bool isFP64bit() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; }
const MipsABIInfo &getABI() const { return ABI; }
bool isABI_N32() const { return ABI.IsN32(); }
bool isABI_N64() const { return ABI.IsN64(); }
bool isABI_O32() const { return ABI.IsO32(); }
- bool isABI_FPXX() const { return STI.getFeatureBits() & Mips::FeatureFPXX; }
+ bool isABI_FPXX() const { return STI.getFeatureBits()[Mips::FeatureFPXX]; }
bool useOddSPReg() const {
- return !(STI.getFeatureBits() & Mips::FeatureNoOddSPReg);
+ return !(STI.getFeatureBits()[Mips::FeatureNoOddSPReg]);
}
bool inMicroMipsMode() const {
- return STI.getFeatureBits() & Mips::FeatureMicroMips;
+ return STI.getFeatureBits()[Mips::FeatureMicroMips];
}
- bool hasMips1() const { return STI.getFeatureBits() & Mips::FeatureMips1; }
- bool hasMips2() const { return STI.getFeatureBits() & Mips::FeatureMips2; }
- bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
- bool hasMips4() const { return STI.getFeatureBits() & Mips::FeatureMips4; }
- bool hasMips5() const { return STI.getFeatureBits() & Mips::FeatureMips5; }
+ bool hasMips1() const { return STI.getFeatureBits()[Mips::FeatureMips1]; }
+ bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; }
+ bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
+ bool hasMips4() const { return STI.getFeatureBits()[Mips::FeatureMips4]; }
+ bool hasMips5() const { return STI.getFeatureBits()[Mips::FeatureMips5]; }
bool hasMips32() const {
- return (STI.getFeatureBits() & Mips::FeatureMips32);
+ return STI.getFeatureBits()[Mips::FeatureMips32];
}
bool hasMips64() const {
- return (STI.getFeatureBits() & Mips::FeatureMips64);
+ return STI.getFeatureBits()[Mips::FeatureMips64];
}
bool hasMips32r2() const {
- return (STI.getFeatureBits() & Mips::FeatureMips32r2);
+ return STI.getFeatureBits()[Mips::FeatureMips32r2];
}
bool hasMips64r2() const {
- return (STI.getFeatureBits() & Mips::FeatureMips64r2);
+ return STI.getFeatureBits()[Mips::FeatureMips64r2];
}
bool hasMips32r3() const {
- return (STI.getFeatureBits() & Mips::FeatureMips32r3);
+ return (STI.getFeatureBits()[Mips::FeatureMips32r3]);
}
bool hasMips64r3() const {
- return (STI.getFeatureBits() & Mips::FeatureMips64r3);
+ return (STI.getFeatureBits()[Mips::FeatureMips64r3]);
}
bool hasMips32r5() const {
- return (STI.getFeatureBits() & Mips::FeatureMips32r5);
+ return (STI.getFeatureBits()[Mips::FeatureMips32r5]);
}
bool hasMips64r5() const {
- return (STI.getFeatureBits() & Mips::FeatureMips64r5);
+ return (STI.getFeatureBits()[Mips::FeatureMips64r5]);
}
bool hasMips32r6() const {
- return (STI.getFeatureBits() & Mips::FeatureMips32r6);
+ return STI.getFeatureBits()[Mips::FeatureMips32r6];
}
bool hasMips64r6() const {
- return (STI.getFeatureBits() & Mips::FeatureMips64r6);
+ return STI.getFeatureBits()[Mips::FeatureMips64r6];
}
+
+ bool hasDSP() const { return STI.getFeatureBits()[Mips::FeatureDSP]; }
+ bool hasDSPR2() const { return STI.getFeatureBits()[Mips::FeatureDSPR2]; }
+ bool hasMSA() const { return STI.getFeatureBits()[Mips::FeatureMSA]; }
bool hasCnMips() const {
- return (STI.getFeatureBits() & Mips::FeatureCnMips);
+ return (STI.getFeatureBits()[Mips::FeatureCnMips]);
}
- bool hasDSP() const { return (STI.getFeatureBits() & Mips::FeatureDSP); }
- bool hasDSPR2() const { return (STI.getFeatureBits() & Mips::FeatureDSPR2); }
- bool hasMSA() const { return (STI.getFeatureBits() & Mips::FeatureMSA); }
bool inMips16Mode() const {
- return STI.getFeatureBits() & Mips::FeatureMips16;
+ return STI.getFeatureBits()[Mips::FeatureMips16];
}
// TODO: see how can we get this info.
bool abiUsesSoftFloat() const { return false; }
diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
index 8849366..c69a60b 100644
--- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
+++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
@@ -36,16 +36,16 @@
public:
MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
: MCDisassembler(STI, Ctx),
- IsMicroMips(STI.getFeatureBits() & Mips::FeatureMicroMips),
+ IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]),
IsBigEndian(IsBigEndian) {}
- bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
- bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; }
+ bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
+ bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; }
bool hasMips32r6() const {
- return STI.getFeatureBits() & Mips::FeatureMips32r6;
+ return STI.getFeatureBits()[Mips::FeatureMips32r6];
}
- bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
+ bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
bool hasCOP3() const {
// Only present in MIPS-I and MIPS-II
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
index 1c2f2da..152399a 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
@@ -112,7 +112,7 @@
}
bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {
- return STI.getFeatureBits() & Mips::FeatureMicroMips;
+ return STI.getFeatureBits()[Mips::FeatureMicroMips];
}
void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const {
@@ -175,7 +175,7 @@
(Opcode != Mips::SLL_MM) && !Binary)
llvm_unreachable("unimplemented opcode in EncodeInstruction()");
- if (STI.getFeatureBits() & Mips::FeatureMicroMips) {
+ if (STI.getFeatureBits()[Mips::FeatureMicroMips]) {
int NewOpcode = Mips::Std2MicroMips (Opcode, Mips::Arch_micromips);
if (NewOpcode != -1) {
if (Fixups.size() > N)
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
index e6d2967..a832698 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
@@ -382,7 +382,7 @@
? true
: false;
- uint64_t Features = STI.getFeatureBits();
+ const FeatureBitset &Features = STI.getFeatureBits();
// Set the header flags that we can in the constructor.
// FIXME: This is a fairly terrible hack. We set the rest
@@ -398,35 +398,35 @@
unsigned EFlags = MCA.getELFHeaderEFlags();
// Architecture
- if (Features & Mips::FeatureMips64r6)
+ if (Features[Mips::FeatureMips64r6])
EFlags |= ELF::EF_MIPS_ARCH_64R6;
- else if (Features & Mips::FeatureMips64r2 ||
- Features & Mips::FeatureMips64r3 ||
- Features & Mips::FeatureMips64r5)
+ else if (Features[Mips::FeatureMips64r2] ||
+ Features[Mips::FeatureMips64r3] ||
+ Features[Mips::FeatureMips64r5])
EFlags |= ELF::EF_MIPS_ARCH_64R2;
- else if (Features & Mips::FeatureMips64)
+ else if (Features[Mips::FeatureMips64])
EFlags |= ELF::EF_MIPS_ARCH_64;
- else if (Features & Mips::FeatureMips5)
+ else if (Features[Mips::FeatureMips5])
EFlags |= ELF::EF_MIPS_ARCH_5;
- else if (Features & Mips::FeatureMips4)
+ else if (Features[Mips::FeatureMips4])
EFlags |= ELF::EF_MIPS_ARCH_4;
- else if (Features & Mips::FeatureMips3)
+ else if (Features[Mips::FeatureMips3])
EFlags |= ELF::EF_MIPS_ARCH_3;
- else if (Features & Mips::FeatureMips32r6)
+ else if (Features[Mips::FeatureMips32r6])
EFlags |= ELF::EF_MIPS_ARCH_32R6;
- else if (Features & Mips::FeatureMips32r2 ||
- Features & Mips::FeatureMips32r3 ||
- Features & Mips::FeatureMips32r5)
+ else if (Features[Mips::FeatureMips32r2] ||
+ Features[Mips::FeatureMips32r3] ||
+ Features[Mips::FeatureMips32r5])
EFlags |= ELF::EF_MIPS_ARCH_32R2;
- else if (Features & Mips::FeatureMips32)
+ else if (Features[Mips::FeatureMips32])
EFlags |= ELF::EF_MIPS_ARCH_32;
- else if (Features & Mips::FeatureMips2)
+ else if (Features[Mips::FeatureMips2])
EFlags |= ELF::EF_MIPS_ARCH_2;
else
EFlags |= ELF::EF_MIPS_ARCH_1;
// Other options.
- if (Features & Mips::FeatureNaN2008)
+ if (Features[Mips::FeatureNaN2008])
EFlags |= ELF::EF_MIPS_NAN2008;
// -mabicalls and -mplt are not implemented but we should act as if they were
@@ -466,7 +466,7 @@
DataSectionData.setAlignment(std::max(16u, DataSectionData.getAlignment()));
BSSSectionData.setAlignment(std::max(16u, BSSSectionData.getAlignment()));
- uint64_t Features = STI.getFeatureBits();
+ const FeatureBitset &Features = STI.getFeatureBits();
// Update e_header flags. See the FIXME and comment above in
// the constructor for a full rundown on this.
@@ -479,10 +479,10 @@
else if (getABI().IsN32())
EFlags |= ELF::EF_MIPS_ABI2;
- if (Features & Mips::FeatureGP64Bit) {
+ if (Features[Mips::FeatureGP64Bit]) {
if (getABI().IsO32())
EFlags |= ELF::EF_MIPS_32BITMODE; /* Compatibility Mode */
- } else if (Features & Mips::FeatureMips64r2 || Features & Mips::FeatureMips64)
+ } else if (Features[Mips::FeatureMips64r2] || Features[Mips::FeatureMips64])
EFlags |= ELF::EF_MIPS_32BITMODE;
// If we've set the cpic eflag and we're n64, go ahead and set the pic
diff --git a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
index 0ed0723..605e74b 100644
--- a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
+++ b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
@@ -355,7 +355,7 @@
uint32_t Inst =
(Bytes[0] << 24) | (Bytes[1] << 16) | (Bytes[2] << 8) | (Bytes[3] << 0);
- if ((STI.getFeatureBits() & PPC::FeatureQPX) != 0) {
+ if (STI.getFeatureBits()[PPC::FeatureQPX]) {
DecodeStatus result =
decodeInstruction(DecoderTableQPX32, MI, Inst, Address, this, STI);
if (result != MCDisassembler::Fail)
diff --git a/llvm/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp b/llvm/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
index fa25f59..4046634 100644
--- a/llvm/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
+++ b/llvm/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
@@ -99,7 +99,7 @@
} else if (IS_VTX(Desc)) {
uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups, STI);
uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset
- if (!(STI.getFeatureBits() & AMDGPU::FeatureCaymanISA)) {
+ if (!(STI.getFeatureBits()[AMDGPU::FeatureCaymanISA])) {
InstWord2 |= 1 << 19; // Mega-Fetch bit
}
@@ -132,7 +132,7 @@
Emit((uint32_t) 0, OS);
} else {
uint64_t Inst = getBinaryCodeForInstr(MI, Fixups, STI);
- if ((STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst) &&
+ if ((STI.getFeatureBits()[AMDGPU::FeatureR600ALUInst]) &&
((Desc.TSFlags & R600_InstFlag::OP1) ||
Desc.TSFlags & R600_InstFlag::OP2)) {
uint64_t ISAOpCode = Inst & (0x3FFULL << 39);
diff --git a/llvm/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp b/llvm/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp
index 5975a51..dc9fb1a 100644
--- a/llvm/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp
+++ b/llvm/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp
@@ -35,7 +35,7 @@
#include "SparcGenAsmWriter.inc"
bool SparcInstPrinter::isV9() const {
- return (STI.getFeatureBits() & Sparc::FeatureV9) != 0;
+ return (STI.getFeatureBits()[Sparc::FeatureV9]) != 0;
}
void SparcInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp
index 543af8e..ed31a58 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp
@@ -262,13 +262,13 @@
MCContext &Ctx, int64_t *Residue);
bool is64BitMode() const {
- return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
+ return STI.getFeatureBits()[X86::Mode64Bit];
}
bool is32BitMode() const {
- return (STI.getFeatureBits() & X86::Mode32Bit) != 0;
+ return STI.getFeatureBits()[X86::Mode32Bit];
}
bool is16BitMode() const {
- return (STI.getFeatureBits() & X86::Mode16Bit) != 0;
+ return STI.getFeatureBits()[X86::Mode16Bit];
}
unsigned getPointerWidth() {
@@ -1073,9 +1073,9 @@
const bool hasCompilerRTSupport = T.isOSLinux();
if (ClAsanInstrumentAssembly && hasCompilerRTSupport &&
MCOptions.SanitizeAddress) {
- if ((STI.getFeatureBits() & X86::Mode32Bit) != 0)
+ if (STI.getFeatureBits()[X86::Mode32Bit] != 0)
return new X86AddressSanitizer32(STI);
- if ((STI.getFeatureBits() & X86::Mode64Bit) != 0)
+ if (STI.getFeatureBits()[X86::Mode64Bit] != 0)
return new X86AddressSanitizer64(STI);
}
return new X86AsmInstrumentation(STI);
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index c24805a6..59d0c1a 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -729,23 +729,24 @@
bool is64BitMode() const {
// FIXME: Can tablegen auto-generate this?
- return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
+ return STI.getFeatureBits()[X86::Mode64Bit];
}
bool is32BitMode() const {
// FIXME: Can tablegen auto-generate this?
- return (STI.getFeatureBits() & X86::Mode32Bit) != 0;
+ return STI.getFeatureBits()[X86::Mode32Bit];
}
bool is16BitMode() const {
// FIXME: Can tablegen auto-generate this?
- return (STI.getFeatureBits() & X86::Mode16Bit) != 0;
+ return STI.getFeatureBits()[X86::Mode16Bit];
}
- void SwitchMode(uint64_t mode) {
- uint64_t oldMode = STI.getFeatureBits() &
- (X86::Mode64Bit | X86::Mode32Bit | X86::Mode16Bit);
- unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(oldMode | mode));
+ void SwitchMode(unsigned mode) {
+ FeatureBitset AllModes({X86::Mode64Bit, X86::Mode32Bit, X86::Mode16Bit});
+ FeatureBitset OldMode = STI.getFeatureBits() & AllModes;
+ unsigned FB = ComputeAvailableFeatures(
+ STI.ToggleFeature(OldMode.flip(mode)));
setAvailableFeatures(FB);
- assert(mode == (STI.getFeatureBits() &
- (X86::Mode64Bit | X86::Mode32Bit | X86::Mode16Bit)));
+
+ assert(FeatureBitset({mode}) == (STI.getFeatureBits() & AllModes));
}
unsigned getPointerWidth() {
@@ -1688,7 +1689,7 @@
}
// rounding mode token
- if (STI.getFeatureBits() & X86::FeatureAVX512 &&
+ if (STI.getFeatureBits()[X86::FeatureAVX512] &&
getLexer().is(AsmToken::LCurly))
return ParseRoundingModeOp(Start, End);
@@ -1746,7 +1747,7 @@
}
case AsmToken::LCurly:{
SMLoc Start = Parser.getTok().getLoc(), End;
- if (STI.getFeatureBits() & X86::FeatureAVX512)
+ if (STI.getFeatureBits()[X86::FeatureAVX512])
return ParseRoundingModeOp(Start, End);
return ErrorOperand(Start, "unknown token in expression");
}
@@ -1756,7 +1757,7 @@
bool X86AsmParser::HandleAVX512Operand(OperandVector &Operands,
const MCParsedAsmOperand &Op) {
MCAsmParser &Parser = getParser();
- if(STI.getFeatureBits() & X86::FeatureAVX512) {
+ if(STI.getFeatureBits()[X86::FeatureAVX512]) {
if (getLexer().is(AsmToken::LCurly)) {
// Eat "{" and mark the current place.
const SMLoc consumedToken = consumeToken();
diff --git a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
index e8c5475..46a6b3c 100644
--- a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
+++ b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
@@ -80,20 +80,19 @@
MCContext &Ctx,
std::unique_ptr<const MCInstrInfo> MII)
: MCDisassembler(STI, Ctx), MII(std::move(MII)) {
- switch (STI.getFeatureBits() &
- (X86::Mode16Bit | X86::Mode32Bit | X86::Mode64Bit)) {
- case X86::Mode16Bit:
+ const FeatureBitset &FB = STI.getFeatureBits();
+ if (FB[X86::Mode16Bit]) {
fMode = MODE_16BIT;
- break;
- case X86::Mode32Bit:
+ return;
+ } else if (FB[X86::Mode32Bit]) {
fMode = MODE_32BIT;
- break;
- case X86::Mode64Bit:
+ return;
+ } else if (FB[X86::Mode64Bit]) {
fMode = MODE_64BIT;
- break;
- default:
- llvm_unreachable("Invalid CPU mode");
+ return;
}
+
+ llvm_unreachable("Invalid CPU mode");
}
struct Region {
diff --git a/llvm/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp b/llvm/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
index 65461af..ec2dc87 100644
--- a/llvm/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
+++ b/llvm/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
@@ -60,7 +60,7 @@
// InstrInfo.td as soon as Requires clause is supported properly
// for InstAlias.
if (MI->getOpcode() == X86::CALLpcrel32 &&
- (getAvailableFeatures() & X86::Mode64Bit) != 0) {
+ getAvailableFeatures()[X86::Mode64Bit]) {
OS << "\tcallq\t";
printPCRelImm(MI, 0, OS);
}
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
index 9b98a3e..7124501 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
@@ -42,15 +42,15 @@
~X86MCCodeEmitter() {}
bool is64BitMode(const MCSubtargetInfo &STI) const {
- return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
+ return STI.getFeatureBits()[X86::Mode64Bit];
}
bool is32BitMode(const MCSubtargetInfo &STI) const {
- return (STI.getFeatureBits() & X86::Mode32Bit) != 0;
+ return STI.getFeatureBits()[X86::Mode32Bit];
}
bool is16BitMode(const MCSubtargetInfo &STI) const {
- return (STI.getFeatureBits() & X86::Mode16Bit) != 0;
+ return STI.getFeatureBits()[X86::Mode16Bit];
}
/// Is16BitMemOperand - Return true if the specified instruction has