Implement initial memory alignment awareness for SSE instructions. Vector loads
and stores that have a specified alignment of less than 16 bytes now use
instructions that support misaligned memory references.
llvm-svn: 40015
diff --git a/llvm/test/CodeGen/X86/sse-align-6.ll b/llvm/test/CodeGen/X86/sse-align-6.ll
new file mode 100644
index 0000000..9b1b781
--- /dev/null
+++ b/llvm/test/CodeGen/X86/sse-align-6.ll
@@ -0,0 +1,8 @@
+; RUN: llvm-as < %s | llc -march=x86-64 | grep movdqu | wc -l | grep 1
+
+define <2 x i64> @bar(<2 x i64>* %p, <2 x i64> %x)
+{
+ %t = load <2 x i64>* %p, align 8
+ %z = mul <2 x i64> %t, %x
+ ret <2 x i64> %z
+}