Implement initial memory alignment awareness for SSE instructions. Vector loads
and stores that have a specified alignment of less than 16 bytes now use
instructions that support misaligned memory references.
llvm-svn: 40015
diff --git a/llvm/test/CodeGen/X86/sse-align-7.ll b/llvm/test/CodeGen/X86/sse-align-7.ll
new file mode 100644
index 0000000..04b013c
--- /dev/null
+++ b/llvm/test/CodeGen/X86/sse-align-7.ll
@@ -0,0 +1,7 @@
+; RUN: llvm-as < %s | llc -march=x86-64 | grep movdqa | wc -l | grep 1
+
+define void @bar(<2 x i64>* %p, <2 x i64> %x)
+{
+ store <2 x i64> %x, <2 x i64>* %p
+ ret void
+}