TableGen support for parameterized register class information
This replaces TableGen's type inference to operate on parameterized
types instead of MVTs, and as a consequence, some interfaces have
changed:
- Uses of MVTs are replaced by ValueTypeByHwMode.
- EEVT::TypeSet is replaced by TypeSetByHwMode.
This affects the way that types and type sets are printed, and the
tests relying on that have been updated.
There are certain users of the inferred types outside of TableGen
itself, namely FastISel and GlobalISel. For those users, the way
that the types are accessed have changed. For typical scenarios,
these replacements can be used:
- TreePatternNode::getType(ResNo) -> getSimpleType(ResNo)
- TreePatternNode::hasTypeSet(ResNo) -> hasConcreteType(ResNo)
- TypeSet::isConcrete -> TypeSetByHwMode::isValueTypeByHwMode(false)
For more information, please refer to the review page.
Differential Revision: https://reviews.llvm.org/D31951
llvm-svn: 313271
diff --git a/llvm/utils/TableGen/CodeGenTarget.h b/llvm/utils/TableGen/CodeGenTarget.h
index ff624ea5..89aa81b 100644
--- a/llvm/utils/TableGen/CodeGenTarget.h
+++ b/llvm/utils/TableGen/CodeGenTarget.h
@@ -17,8 +17,10 @@
#ifndef LLVM_UTILS_TABLEGEN_CODEGENTARGET_H
#define LLVM_UTILS_TABLEGEN_CODEGENTARGET_H
+#include "CodeGenHwModes.h"
#include "CodeGenInstruction.h"
#include "CodeGenRegisters.h"
+#include "InfoByHwMode.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/TableGen/Record.h"
#include <algorithm>
@@ -69,7 +71,8 @@
std::unique_ptr<CodeGenInstruction>> Instructions;
mutable std::unique_ptr<CodeGenRegBank> RegBank;
mutable std::vector<Record*> RegAltNameIndices;
- mutable SmallVector<MVT::SimpleValueType, 8> LegalValueTypes;
+ mutable SmallVector<ValueTypeByHwMode, 8> LegalValueTypes;
+ CodeGenHwModes CGH;
void ReadRegAltNameIndices() const;
void ReadInstructions() const;
void ReadLegalValueTypes() const;
@@ -128,22 +131,18 @@
/// getRegisterVTs - Find the union of all possible SimpleValueTypes for the
/// specified physical register.
- std::vector<MVT::SimpleValueType> getRegisterVTs(Record *R) const;
+ std::vector<ValueTypeByHwMode> getRegisterVTs(Record *R) const;
- ArrayRef<MVT::SimpleValueType> getLegalValueTypes() const {
- if (LegalValueTypes.empty()) ReadLegalValueTypes();
+ ArrayRef<ValueTypeByHwMode> getLegalValueTypes() const {
+ if (LegalValueTypes.empty())
+ ReadLegalValueTypes();
return LegalValueTypes;
}
- /// isLegalValueType - Return true if the specified value type is natively
- /// supported by the target (i.e. there are registers that directly hold it).
- bool isLegalValueType(MVT::SimpleValueType VT) const {
- ArrayRef<MVT::SimpleValueType> LegalVTs = getLegalValueTypes();
- return is_contained(LegalVTs, VT);
- }
-
CodeGenSchedModels &getSchedModels() const;
+ const CodeGenHwModes &getHwModes() const { return CGH; }
+
private:
DenseMap<const Record*, std::unique_ptr<CodeGenInstruction>> &
getInstructions() const {