| commit | 77d0b88999a0ad707597d9aba4ae2e43f08a97d4 | [log] [tgz] |
|---|---|---|
| author | Andrew Trick <atrick@apple.com> | Fri Jun 22 02:50:33 2012 +0000 |
| committer | Andrew Trick <atrick@apple.com> | Fri Jun 22 02:50:33 2012 +0000 |
| tree | 728ca05747ec6168425d0c3bf4ecacfc733858ae | |
| parent | 3ccb1b8cf9077c99e19b4582d8619d7616ad2fd0 [diff] |
ARM scheduling fix: don't guess at implicit operand latency. This is a minor drive-by fix with no robust way to unit test. As an example see neon-div.ll: SU(16): %Q8<def> = VMOVLsv4i32 %D17, pred:14, pred:%noreg, %Q8<imp-use,kill> val SU(1): Latency=2 Reg=%Q8 ...should be latency=1 llvm-svn: 158960