[RISCV] Specify registers used for exception handling
Implements the handling of __builtin_eh_return_regno().
Differential Revision: https://reviews.llvm.org/D63417
Patch by Edward Jones.
llvm-svn: 365305
diff --git a/clang/test/CodeGen/builtins-riscv.c b/clang/test/CodeGen/builtins-riscv.c
new file mode 100644
index 0000000..5297c42
--- /dev/null
+++ b/clang/test/CodeGen/builtins-riscv.c
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 -Wall -Werror -triple riscv32 -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: %clang_cc1 -Wall -Werror -triple riscv64 -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+
+void test_eh_return_data_regno() {
+ // CHECK: store volatile i32 10
+ // CHECK: store volatile i32 11
+ volatile int res;
+ res = __builtin_eh_return_data_regno(0);
+ res = __builtin_eh_return_data_regno(1);
+}