commit 782c03bb7e80dc96043ee1d44bea8fcbb467cf76
author Matt Arsenault <Matthew.Arsenault@amd.com> Tue Nov 03 22:30:13 2015 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Tue Nov 03 22:30:13 2015 +0000
tree af3ad877759bec9380f8148efb8660baa7888cb6
parent d9d659aa2317bab47e06b5733ef7caa98fe62051

AMDGPU: Initialize SIFixSGPRCopies so -print-after works

llvm-svn: 251995

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 14f28d1..ab40d17 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -45,6 +45,7 @@
 
   PassRegistry *PR = PassRegistry::getPassRegistry();
   initializeSILowerI1CopiesPass(*PR);
+  initializeSIFixSGPRCopiesPass(*PR);
   initializeSIFoldOperandsPass(*PR);
   initializeSIFixSGPRLiveRangesPass(*PR);
   initializeSIFixControlFlowLiveIntervalsPass(*PR);
@@ -276,7 +277,7 @@
 bool GCNPassConfig::addInstSelector() {
   AMDGPUPassConfig::addInstSelector();
   addPass(createSILowerI1CopiesPass());
-  addPass(createSIFixSGPRCopiesPass(*TM));
+  addPass(&SIFixSGPRCopiesID);
   addPass(createSIFoldOperandsPass());
   return false;
 }