Handle vector move / load which zero the destination register top bits (i.e. movd, movq, movss (addr), movsd (addr)) with X86 specific dag combine.
llvm-svn: 50838
diff --git a/llvm/test/CodeGen/X86/vec_set-6.ll b/llvm/test/CodeGen/X86/vec_set-6.ll
index 1eeedf1..02df526 100644
--- a/llvm/test/CodeGen/X86/vec_set-6.ll
+++ b/llvm/test/CodeGen/X86/vec_set-6.ll
@@ -1,5 +1,6 @@
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -o %t -f
-; RUN: grep unpcklps %t | count 1
+; RUN: grep movss %t | count 1
+; RUN: grep movups %t | count 1
; RUN: grep shufps %t | count 1
define <4 x float> @test(float %a, float %b, float %c) nounwind {