commit 79e38cde37e827463e8231734926072415ee1d8e
author Akira Hatanaka <ahatanaka@mips.com> Fri Sep 06 23:52:46 2013 +0000
committer Akira Hatanaka <ahatanaka@mips.com> Fri Sep 06 23:52:46 2013 +0000
tree 4254c652d0d9f6052d15796d1ebac78c3ff49fd5
parent 215f96c084a2456ba9cc8717cb5758b5f04eef15

[mips] Define "trap" as a pseudo instruction that turns into "break 0, 0".

llvm-svn: 190224

llvm/lib/Target/Mips/MipsCodeEmitter.cpp

diff --git a/llvm/lib/Target/Mips/MipsCodeEmitter.cpp b/llvm/lib/Target/Mips/MipsCodeEmitter.cpp
index 0f1917a..b50edf1 100644
--- a/llvm/lib/Target/Mips/MipsCodeEmitter.cpp
+++ b/llvm/lib/Target/Mips/MipsCodeEmitter.cpp
@@ -327,6 +327,10 @@
     BuildMI(MBB, &*MI, MI->getDebugLoc(), II->get(Mips::BEQ)).addReg(Mips::ZERO)
       .addReg(Mips::ZERO).addOperand(MI->getOperand(0));
     break;
+  case Mips::TRAP:
+    BuildMI(MBB, &*MI, MI->getDebugLoc(), II->get(Mips::BREAK)).addImm(0)
+      .addImm(0);
+    break;
   case Mips::JALRPseudo:
     BuildMI(MBB, &*MI, MI->getDebugLoc(), II->get(Mips::JALR), Mips::RA)
       .addReg(MI->getOperand(0).getReg());