Go ahead and emit the barrier on x86-64 even without sse2. The
processor supports it just fine.
Fixes PR9675 and rdar://9740801
llvm-svn: 134664
diff --git a/llvm/test/CodeGen/X86/membarrier.ll b/llvm/test/CodeGen/X86/membarrier.ll
new file mode 100644
index 0000000..42f8ef5
--- /dev/null
+++ b/llvm/test/CodeGen/X86/membarrier.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86-64 -mattr=-sse -O0
+; PR9675
+
+define i32 @t() {
+entry:
+ %i = alloca i32, align 4
+ store i32 1, i32* %i, align 4
+ call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true)
+ %0 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %i, i32 1)
+ call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true)
+ ret i32 0
+}
+
+declare i32 @llvm.atomic.load.sub.i32.p0i32(i32* nocapture, i32) nounwind
+declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind